設計工具
ISO5852S
- 100-kV/µs Minimum Common-Mode Transient Immunity (CMTI) at V CM = 1500 V
- Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
- Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
- 2-A Active Miller Clamp
- Output Short-Circuit Clamp
- Soft Turn-Off (STO) during Short Circuit
- Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
- Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
- Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
- 2.25-V to 5.5-V Input Supply Voltage
- 15-V to 30-V Output Driver Supply Voltage
- CMOS Compatible Inputs
- Rejects Input Pulses and Noise Transients Shorter Than 20 ns
- Operating Temperature: –40°C to +125°C Ambient
- Isolation Surge Withstand Voltage 12800-V PK
- Safety-Related Certifications:
- 8000-V PK V IOTM and 2121-V PK V IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
- 5700-V RMS Isolation for 1 Minute per UL 1577
- CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
- TUV Certification per EN 61010-1 and EN 60950-1
- GB4943.1-2011 CQC Certification
The ISO5852S device is a 5.7-kV RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.
An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V EE2, the gate-driver output is pulled hard to the V EE2 potential, turning the IGBT immediately off.
When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.
When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.
The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.
The ISO5852S device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.
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開發板
ISO5852SDWEVM-017 — 適用於 SiC 和 IGBT 電源模組的驅動和保護評估板
The ISO5852SDWEVM-017 is a compact, dual chanel isolated gate driver board providing drive, bias voltages, protection and diagnostic needed for half-bridge Sic MOSFET and IGBT Power Modules in standard 62-mm package. This TI EVM is based on 5.7-kVrms reinforced isolation driver IC ISO5852SDW in (...)
使用指南: PDF
開發板
ISO5852SEVM — 強化型隔離式 IGBT 閘極驅動器評估模組
This evaluation module, featuring ISO5852S reinforced isolated gate driver device, allows designers to evaluate device AC and DC performance with a pre-populated 1-nF load or with a user-installed IGBT in either of the standard TO-247 or TO-220 packages.
使用指南: PDF
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計
TIDA-01606 — 10-kW、雙向三相三級 (T 型) 逆變器和 PFC 參考設計
This verified reference design provides an overview on how to implement a three-level three-phase SiC based DC:AC T-type inverter stage. Higher switching frequency of 50KHz reduces the size of magnetics for the filter design and enables higher power density. The use of SiC MOSFETs with switching (...)
參考設計
TIDA-00195 — 適用於 3 相逆變器系統的絕緣式 IGBT 閘極驅動器評估平台參考設計
The TIDA-00195 reference design consists of a 22kW power stage with TI’s new reinforced isolated IGBT gate driver ISO5852S intended for motor control in various applications. This design allows performance evaluation of the ISO5852S in 3-phase inverter incorporating 1200V rated IGBT modules (...)
參考設計
TIDA-01599 — TÜV SÜD 評估工業驅動器的安全扭矩關閉 (STO) 參考設計 (IEC 61800-5-2)
本參考設計概述具有 CMOS 輸入隔離式 IGBT 閘極驅動器的三相逆變器的安全扭矩關閉 (STO) 子系統。STO 子系統採用雙通道架構 (1oo2)，硬體容錯範圍爲 1 (HFT=1)。實作時遵循去能脫扣概念。當雙 STO 輸入 (STO_1 和 STO_2) 變低電位作動時，六個隔離 IGBT 柵極驅動器的一次和二次側對應電源供電將透過負載開關切斷。如此可消除控制馬達並為馬達通電的可能性。STO 參考設計 (1oo2) 已由 TÜV SÜD 進行評估，一般適用於 SIL 3 和 PL e/Cat。3.
參考設計
TIDA-00917 — 適用於具有短路保護功能和電流緩衝器的並聯 IGBT 的閘極驅動器參考設計
Paralleling insulated-gate bipolar transistors (IGBTs) becomes necessary for power conversion equipment with higher output power ratings, where a single IGBT cannot provide the required load current. This reference design implements a reinforced isolated IGBT gate control module to drive (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (DW) | 16 | Ultra Librarian |
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