LM2104
- Drives two N-channel MOSFETs in half-bridge configuration
- 8-V typical undervoltage lockout on GVDD
- 107-V absolute maximum voltage on BST
- –19.5-V absolute maximum negative transient voltage handling on SH
- 0.5-A/0.8-A peak source/sink currents
- 475-ns typical fixed internal dead-time
- Built-in cross conduction prevention
- 115-ns typical propagation delay
- Shutdown logic input pin SD
- Single input pin IN
The LM2104 is a compact, high-voltage gate driver designed to drive both the high-side and the low-side N-channel MOSFETs in a synchronous buck or a half-bridge configuration. The IN pin allows the device to be used in single PWM input applications, and the SD pin allows the controller to disable the drivers outputs by turning them off when the SD pin is low, regardless of the IN pin state.
The fixed dead-time and the –1-V DC and –19.5-V transient negative voltage handling on the SH pin improve the system robustness in high noise applications. The LM2104 is available in an 8-pin SOIC package compatible with industry standard pinouts. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails for protection during power up and power down.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | LM2104 107-V, 0.5-A, 0.8-A Half-Bridge Driver with8-V UVLO, Dead Time, and Shutdown Pin datasheet (Rev. A) | PDF | HTML | 2023年 10月 3日 |
Application note | How to Choose a Gate Driver for DC Motor Drives | PDF | HTML | 2023年 10月 5日 | |
Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020年 2月 28日 | ||
Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020年 2月 28日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOIC (D) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點