封裝資訊
| 封裝 | 針腳 CDIP (JT) | 24 |
| 操作溫度範圍 (°C) -55 to 125 |
| 包裝數量 | 運送業者 15 | TUBE |
SN54BCT8373A 的特色
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Octal Test-Integrated Circuits
- Functionally Equivalent to 'F373 and 'BCT373 in the Normal-Function Mode
- Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
- Test Operation Synchronous to Test Access Port (TAP)
- Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V) on TMS Pin
- SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
- Parallel Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Package Options Include Plastic Small-Outline (DW) Packages,
Ceramic Chip Carriers (FK), and Standard Plastic and Ceramic
300-mil DIPs (JT, NT)
SCOPE is a trademark of Texas Instruments Incorporated.
SN54BCT8373A 的說明
The 'BCT8373A scan test devices with octal D-type latches are
members of the Texas Instruments SCOPETM testability
integrated-
circuit family. This family of devices supports IEEE Standard
1149.1-1990 boundary scan to facilitate testing of complex circuit
board assemblies. Scan access to the test circuitry is accomplished
via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F373 and 'BCT373 octal D-type latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal latches.
In the test mode, the normal operation of the SCOPETM octal latches is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations, as described in IEEE Standard 1149.1-1990.
Four dedicated test terminals are used to control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8373A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8373A is characterized for operation from 0°C to 70°C.