SN74F543
- 3-State True Outputs
- Back-to-Back Registers for Storage
- Package Options Include Plastic Small-Outline and Shrink Small-Outline Packages and Standard Plastic 300-mil DIPs
The SN74F543 octal transceiver contains two sets of D-type latches
for temporary storage of data flowing in either direction. Separate
latch-enable (
or 
) and output enable (
or 
) inputs are provided for each register to permit
independent control in either direction of data flow. The A outputs
are characterized to sink 24 mA while the B outputs are characterized
to sink 64 mA.
The A-to-B enable (
)
input must be low in order to enter data from A or to output data
from B. Having low and low makes the A-to-B latches
transparent; a subsequent low-to-high transition of puts the A latches in the storage
mode. With and both low, the 3-state B outputs
are active and reflect the data present at the output of the A
latches. Data flow from B to A is similar, but requires using the
, , and inputs.
The SN74F543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN74F543 is characterized for operation from 0°C to 70°C.
A-to-B data flow is shown; B-to-A flow control is the same
except that it uses ,
, and .
Output level before the indicated steady-state input conditions were established.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Octal Registered Transceiver With 3-State Outputs datasheet (Rev. B) | 1993年 10月 1日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997年 8月 1日 | ||
| Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (DW) | 24 | Ultra Librarian |
| SSOP (DB) | 24 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點