SN74HC595

現行

具有 3 態輸出暫存器的 8 位元移位暫存器

產品詳細資料

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOIC (DW) 16 106.09 mm² 10.3 x 10.3 SOP (NS) 16 79.56 mm² 10.2 x 7.8 SSOP (DB) 16 48.36 mm² 6.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4 — (—) See data sheet
  • 8-bit serial-in, parallel-out shift
  • Wide operating voltage range of 2 V to 6 V
  • High-current 3-state outputs can drive up to 15 LSTTL loads
  • Low power consumption: 80-µA (maximum) ICC
  • tpd = 13 ns (typical)
  • ±6-mA output drive at 5 V
  • Low input current: 1 µA (maximum)
  • Shift register has direct clear
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • 8-bit serial-in, parallel-out shift
  • Wide operating voltage range of 2 V to 6 V
  • High-current 3-state outputs can drive up to 15 LSTTL loads
  • Low power consumption: 80-µA (maximum) ICC
  • tpd = 13 ns (typical)
  • ±6-mA output drive at 5 V
  • Low input current: 1 µA (maximum)
  • Shift register has direct clear
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

The SNx4HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

The SNx4HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

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類型 標題 日期
* Data sheet SNx4HC595 8-Bit Shift Registers With 3-State Output Registers datasheet (Rev. J) PDF | HTML 2021年 10月 7日
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Application note Optimizing Network Switch Designs with Common Logic Use Cases (Rev. A) PDF | HTML 2021年 4月 1日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Technical article How to create a dynamic power solution for stepper motors, relays and LEDs PDF | HTML 2016年 11月 1日
User guide BOOSTXL-ULN2003 Dual Stepper Motor Driver BoosterPack Hardware 2016年 4月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996年 5月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

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Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOIC (DW) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
SSOP (DB) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
— (—)

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