封裝資訊
| 封裝 | 針腳 TSSOP (PW) | 14 |
| 操作溫度範圍 (°C) -40 to 85 |
| 包裝數量 | 運送業者 2,000 | LARGE T&R |
SN74LV125AT 的特色
- Inputs Are TTL-Voltage Compatible
- 4.5-V to 5.5-V V CC Operation
- Typical t pd of 3.8 ns at 5 V
- Typical V OLP (Output Ground Bounce) < 0.8 V at V CC = 5 V, T A = 25°C
- Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 5 V, T A = 25°C
- Support Mixed-Mode Voltage Operation on All Ports
- I off Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
SN74LV125AT 的說明
The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high.