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SN74LVC16244A

現行

具有 3 態輸出的 16 通道 1.65-V 至 3.6-V 緩衝器

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產品規格表

SN74LVC16244A

現行
產品規格表 立即訂購

產品詳細資料

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 24 Supply current (max) (µA) 20 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 24 Supply current (max) (µA) 20 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Member of the Texas Instruments
    Widebus Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.1 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Supports Mixed-Mode Signal Operation on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
  • Member of the Texas Instruments
    Widebus Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.1 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Supports Mixed-Mode Signal Operation on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.

The SN74LVC16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74LVC16244A device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The device provides true outputs and symmetrical active-low output-enable (OE) inputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.

The SN74LVC16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74LVC16244A device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The device provides true outputs and symmetrical active-low output-enable (OE) inputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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SN74AUC16244 現行 具有 3 態輸出的 16 通道、0.8-V 至 2.7-V 高速緩衝器 Smaller voltage range (0.8V to 2.7V), shorter average propagation delay (1.7ns)
功能與所比較的裝置相似
SN74LVC244A 現行 具有 3 態輸出的 8 通道 1.65-V 至 3.6-V 緩衝器 Voltage range 1.65V to 3.6V, average propagation delay 5.5ns, average drive strength 24mA

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類型 標題 日期
* Data sheet SN74LVC16244A 16-Bit Buffer/Driver With 3-State Outputs datasheet (Rev. C) PDF | HTML 2014年 1月 28日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003年 11月 6日
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002年 12月 18日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002年 3月 27日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note LVC Characterization Information 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

SN74LVC16244A Behavioral SPICE Model

SCAM107.ZIP (7 KB) - PSpice Model
下載
模擬型號

SN74LVC16244A IBIS Model

SCEM228.ZIP (42 KB) - IBIS Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
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