韌體
產品規格表
TCA6424A
- Operating power-supply voltage range of 1.65 V to 5.5 V
- Allows bidirectional voltage-level translation and GPIO expansion between:
- 1.8-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- 2.5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- 3.3-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- 5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- I2C to Parallel port expander
- Low standby current consumption of 1 µA
- Schmitt-Trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs
- Vhys = 0.18 V Typ at 1.8 V
- Vhys = 0.25 V Typ at 2.5 V
- Vhys = 0.33 V Typ at 3.3 V
- Vhys = 0.5 V Typ at 5 V
- 5-V Tolerant I/O ports
- Active-low reset input ( RESET)
- Open-drain active-low interrupt output ( INT)
- 400-kHz Fast I2C Bus
- Input/output configuration register
- Polarity inversion register
- Internal power-on reset
- Power up with all channels configured as inputs
- No glitch on power up
- Noise filter on SCL/SDA inputs
- Latched outputs with high-current drive maximum capability for directly driving LEDs
- Latch-up performance exceeds 100 mA per JESD 78, class II
- ESD protection exceeds JESD 22
- 2000-V Human-body model (A114-A)
- 200-V Machine model (A115-A)
- 1000-V Charged-device model (C101)
The bidirectional voltage level translation in the TCA6424A is provided through VCCI. VCCI should be connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6424A. The voltage level on the P-port of the TCA6424A is determined by the VCCP.
The TCA6424A consists of three 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system controller.
The system controller can reset the TCA6424A in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
The TCA6424A open-drain interrupt ( INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system controller that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA6424A can remain a simple target device.
The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to share the same I2C bus or SMBus.
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 9 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | TCA6424A Low-Voltage 24-Bit I2C and SMBus I/O Expander With Interrupt Output, Reset, and Configuration Registers datasheet (Rev. D) | PDF | HTML | 2023年 1月 30日 |
| Application note | I2C: What is the Auto Increment Feature? | PDF | HTML | 2024年 7月 5日 | |
| Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024年 7月 3日 | |
| Application note | I2C Dynamic Addressing | 2019年 4月 25日 | ||
| Application note | Choosing the Correct I2C Device for New Designs | PDF | HTML | 2016年 9月 7日 | |
| Selection guide | I2C Infographic Flyer | 2015年 12月 3日 | ||
| Application note | Understanding the I2C Bus | PDF | HTML | 2015年 6月 30日 | |
| Application note | I2C Bus Pull-Up Resistor Calculation | PDF | HTML | 2015年 2月 13日 | |
| EVM User's guide | I/O Expander EVM User's Guide (Rev. A) | 2014年 7月 25日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
BOOSTXL-IOLINKM-8 — 八埠 IO-Link 主要裝置 BoosterPack™
此 BoosterPack™ 專為搭配 LP-AM243 TI LaunchPad™ 套件及 Sitara™ AM243x MCU 運作。此設計採用具快速且決定性時脈、獨立週期與位元率配置的八埠 IO-Link 主要裝置。此設計可用於建立遠端 IO 閘道，以連接 OPC UA、Profinet、EtherCAT 或乙太網路 IP。適用 Sitara ™ 處理器基礎訊框處理程式的可編程即時單元 (PRU) 可提供靈活的時脈與同步控制方式。
使用指南: PDF
設計工具
I2C-DESIGNER — I2C 設計工具
Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard (...)
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
參考設計
TIDA-00426 — 12 Gbps 多通道 BERT 板參考設計
This reference design is a 12-Gbps low-cost bit error tester (BERT) capable of generating and checking up to 8 channels of pseudo-random binary sequences (PRBS). This validated design is a convenient way to generate multi-channels high speed serial bit streams of up to 12-Gbps, and checking (...)
參考設計
TIDA-00609 — 自我啟動音訊系統
The purpose of this reference design is to provide hardware and software tools that can be used as reference for audio systems. The new revision of the PurePath™ Console Motherboard (Rev F) adds stand-alone self-booting capabilities to allow making compelling demos with any evaluation module (...)
參考設計
TIDA-00352 — SDI 視訊聚合參考設計
This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| UQFN (RGJ) | 32 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。