TL7700-SEP
- VID V62/19602
- Radiation hardened
- Single event latch-up (SEL) immune to 43 MeV-cm2/mg at 125°C
- Total ionizing dose (TID) RLAT for every wafer lot up to 20 krad(Si)
- Space enhanced plastic
- Controlled baseline
- Gold wire
- NiPdAu lead finish
- One assembly and test site
- One fabrication site
- Available in military (–55°C to 125°C) temperature range
- Extended product life cycle
- Extended product-change notification
- Product traceability
- Enhanced mold compound for low outgassing
- Adjustable sense voltage with two external resistors
- 1% sense voltage tolerance (25°C)
- Adjustable hysteresis of sense voltage
- Wide operating supply-voltage range: 1.8 V to 40 V
- Low power consumption: ICC = 0.6 mA typical, VCC = 40 V
The TL7700-SEP is a bipolar integrated circuit designed for use as a reset controller in microcomputer and microprocessor systems. The SENSE voltage can be set to any value greater than 0.5 V using two external resistors.
Circuit function is very stable, with supply voltage in the 1.8-V to 40-V range. Minimum supply current allows use with AC line operation and portable battery operation. The TL7700-SEP device is designed for operation from –55°C to 125°C.
技術文件
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開發板
ALPHA-3P-ADM-VA601-SPACE-AMD — Alpha Data ADM-VA601 套件,使用 AMD Versal 核心 XQRVC1902 ACAP 和 TI 耐輻射產品
外型尺寸採用 6U VPX,強調 AMD-Xilinx® Versal AI Core XQRVC1902 適應性 SoC/FPGA。ADM-VA600 為模組化機板設計,配備一個 FMC+ 連接器、DDR4 DRAM 及系統監控。零組件多數為耐輻射電源管理、介面、時脈與嵌入式處理裝置。
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
TSSOP (PW) | 8 | Ultra Librarian |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點