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微控制器 (MCU) 與處理器
數位訊號處理器 (DSP)

TMS320C6412

現行

C64x 定點 DSP - 高達 720MHz、McBSP、McASP、I2cC、乙太網路

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TMS320C6412

現行
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產品詳細資料

DSP type 1 C64x DSP (max) (MHz) 500, 600, 720 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 PCIe 1 PCI Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C64x DSP (max) (MHz) 500, 600, 720 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 PCIe 1 PCI Rating Catalog Operating temperature range (°C) -40 to 105
OMFCBGA (GDK) 548 529 mm² 23 x 23 OMFCBGA (GNZ) 548 729 mm² 27 x 27 OMFCBGA (ZDK) 548 529 mm² 23 x 23 OMFCBGA (ZNZ) 548 729 mm² 27 x 27
  • High-Performance Digital Media Processor (TMS320C6412)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-500)
  • 3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
  • High-Performance Digital Media Processor (TMS320C6412)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-500)
  • 3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code
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類型 標題 日期
* Data sheet TMS320C6412 Fixed-Point Digital Signal Processor datasheet (Rev. J) 2010年 10月 12日
* Errata TMS320C6412 DSP Silicon Errata (Silicon Revisions 2.0, 1.2, 1.1, 1.0) (Rev. J) 2010年 2月 4日
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021年 5月 19日
User guide Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012年 8月 9日
Application note Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010年 7月 30日
User guide TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009年 7月 2日
Application note TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 2007年 9月 4日
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007年 5月 20日
User guide TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 2007年 4月 11日
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007年 4月 4日
User guide TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 2007年 3月 26日
User guide TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (Rev. C) 2007年 1月 25日
User guide TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 2006年 12月 14日
User guide TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 2006年 11月 15日
User guide TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) 2006年 2月 28日
User guide TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 2006年 1月 1日
Application note TMS320C6412 Hardware Designer's Resource Guide (Rev. A) 2005年 10月 21日
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 2005年 10月 20日
User guide TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 2005年 3月 1日
Application note TMS320C6412 Power Consumption Summary (Rev. E) 2005年 1月 27日
User guide TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 2005年 1月 25日
Application note Use and Handling of Semiconductor Packages With ENIG Pad Finishes 2004年 8月 31日
User guide TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 2004年 8月 13日
Application note TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 2004年 4月 26日
Application note TMS320C6000 Board Design: Considerations for Debug (Rev. C) 2004年 4月 21日
User guide TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A) 2004年 3月 26日
User guide TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 2004年 3月 25日
Application note TMS320C6000 McBSP Initialization (Rev. C) 2004年 3月 8日
Application note TMS320C6000 EDMA IO Scheduling and Performance 2004年 3月 5日
Application note TMS320C64x EDMA Performance Data 2004年 3月 5日
Application note TMS320C64x EDMA Architecture 2004年 3月 3日
Application note TMS320C64x DSP Peripheral Component Interconnect (PCI) Performance 2003年 10月 31日
Application note TMS320C64x DSP Host Port Interface (HPI) Performance 2003年 10月 24日
User guide TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 2003年 7月 31日
User guide TMS320C6000 DSP Cache User's Guide (Rev. A) 2003年 5月 5日
Application note Using IBIS Models for Timing Analysis (Rev. A) 2003年 4月 15日
Application note TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 2002年 6月 4日
Application note TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 2002年 4月 17日
Application note TMS320C6000 Board Design for JTAG (Rev. C) 2002年 4月 2日
Application note TMS320C6000 EMIF to External Flash Memory (Rev. A) 2002年 2月 13日
Application note Cache Usage in High-Performance DSP Applications with the TMS320C64x 2001年 12月 13日
Application note Using a TMS320C6000 McBSP for Data Packing (Rev. A) 2001年 10月 31日
Application note TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 2001年 10月 24日
Application note Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 2001年 9月 30日
Application note TMS320C6000 Host Port to MC68360 Interface (Rev. A) 2001年 9月 30日
Application note TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 2001年 8月 31日
Application note TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 2001年 8月 31日
Application note Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 2001年 8月 31日
Application note TMS320C6000 System Clock Circuit Example (Rev. A) 2001年 8月 15日
Application note TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 2001年 7月 23日
Application note TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 2001年 7月 10日
Application note TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 2001年 6月 30日
Application note TMS320C6000 Host Port to MPC860 Interface (Rev. A) 2001年 6月 21日
Application note TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 2001年 5月 21日
User guide TMS320C64x Technical Overview (Rev. B) 2001年 1月 30日
Application note Circular Buffering on TMS320C6000 (Rev. A) 2000年 9月 12日
Application note TMS320C6000 McBSP as a TDM Highway (Rev. A) 2000年 9月 11日
Application note TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 2000年 2月 2日
Application note General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 2000年 1月 31日
Application note TMS320C6000 C Compiler: C Implementation of Intrinsics 1999年 12月 7日
Application note TMS320C6000 McBSP: I2S Interface 1999年 9月 8日

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TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

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TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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SPRC090 — Download TMS320C6000 Chip Support Library

The Chip Support Library (CSL) provides an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use, compatibility between various C6000 devices and hardware abstraction. This will shorten development time by providing standardization (...)
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TMS320C6412 — C64x 定點 DSP - 高達 720MHz、McBSP、McASP、I2cC、乙太網路 TMS320C6414 — C64x 定點 DSP - 高達 720MHz、McBSP TMS320C6414T — C64x 定點 DSP - 高達 1GHz、McBSP TMS320C6415 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI TMS320C6415T — C64x 定點 DSP - 高達 850MHz、McBSP、PCI TMS320C6416 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI、VCP/TCP TMS320C6416T — C64x 定點 DSP - 高達 850MHz、McBSP、PCI、VCP/TCP TMS320C6701 — C67x 浮點 DSP - 高達 167MHz、McBSP TMS320DM640 — 視訊/成像定點數位訊號處理器 TMS320DM641 — 視訊/成像定點數位訊號處理器 TMS320DM642 — 視訊/成像定點數位訊號處理器 TMS320DM642Q — 視訊/成像定點數位訊號處理器
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SPRC122 — C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

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產品
數位訊號處理器 (DSP)
SM320C6201-EP — 增強型產品 C6201 定點 DSP SM320C6455-EP — 強化型產品 C6455 定點 DSP SMJ320C6201B — 軍用定點數位訊號處理器 SMJ320C6203 — 軍用級 C62x 定點 DSP - 陶瓷封裝 TMS320C6202B — C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B — C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 — 定點數位訊號處理器 TMS320C6205 — 定點數位訊號處理器 TMS320C6211B — C62x 定點 DSP - 高達 167MHz TMS320C6412 — C64x 定點 DSP - 高達 720MHz、McBSP、McASP、I2cC、乙太網路 TMS320C6414 — C64x 定點 DSP - 高達 720MHz、McBSP TMS320C6414T — C64x 定點 DSP - 高達 1GHz、McBSP TMS320C6415 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI TMS320C6415T — C64x 定點 DSP - 高達 850MHz、McBSP、PCI TMS320C6416 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI、VCP/TCP TMS320C6416T — C64x 定點 DSP - 高達 850MHz、McBSP、PCI、VCP/TCP TMS320C6421 — C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2、SDRAM TMS320C6421Q — C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424 — C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2、SDRAM TMS320C6424Q — C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6452 — C64x+ 定點 DSP - 高達 900MHz、1Gbps 乙太網路 TMS320C6454 — C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6455 — C64x+ 定點 DSP 最高 1.2GHz、64 位元 EMIFA、32 與 16 位元 DDR2、1Gbps 乙太網路 TMS320C6457 — 通訊基礎設施數位訊號處理器 TMS320C6474 — 多核數位訊號處理器 TMS320DM640 — 視訊/成像定點數位訊號處理器 TMS320DM641 — 視訊/成像定點數位訊號處理器 TMS320DM642 — 視訊/成像定點數位訊號處理器 TMS320DM642Q — 視訊/成像定點數位訊號處理器 TMS320DM6431 — 數位媒體處理器 TMS320DM6431Q — 數位媒體處理器，高達 2400 MIPS、300 MHz 時脈速率 TMS320DM6433 — 數位媒體處理器 TMS320DM6435 — 數位媒體處理器 TMS320DM6435Q — 數位媒體處理器，最高達 4800 MIPS、600 MHz 時脈速率、1 McASP、1 McBSP TMS320DM6437 — 數位媒體處理器 TMS320DM6437Q — 數位媒體處理器，最高達 4800 MIPS、600 MHz 時脈速率、1 個 McASP、2 個 McBSP TMS320DM6441 — DaVinci 數位媒體晶片系統 TMS320DM6443 — DaVinci 數位媒體晶片系統 TMS320DM6446 — DaVinci 數位媒體晶片系統
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驅動程式或資料庫

SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
使用指南: PDF
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驅動程式或資料庫

SPRC265 — TMS320C6000 DSP 庫 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
使用指南: PDF
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驅動程式或資料庫

TELECOMLIB — 電信和媒體庫 - 用於 TMS320C64x+ 和 TMS320C55x 處理器的 FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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軟體轉碼器

ADT-3P-DSPVOIPCODECS — 適應性數位技術 DSP VOIP、語音和音訊轉碼器

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
從：Adaptive Digital Technologies, Inc.
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軟體轉碼器

VOCAL-3P-DSPVOIPCODECS — VOCAL 技術 DSP VoIP 轉碼器

With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)
從：VOCAL Technologies, Ltd.
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模擬型號

C6412 GDK BSDL Model

SPRM123.ZIP (9 KB) - BSDL Model
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模擬型號

C6412 GDK/GNZ IBIS Model

SPRM110.ZIP (109 KB) - IBIS Model
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模擬型號

C6412 GNZ BSDL Model

SPRM122.ZIP (9 KB) - BSDL Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
OMFCBGA (GDK) 548 Ultra Librarian
OMFCBGA (GNZ) 548 Ultra Librarian
OMFCBGA (ZDK) 548 Ultra Librarian
OMFCBGA (ZNZ) 548 Ultra Librarian
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