產品詳細資料

DSP type 1 C64x DSP (max) (MHz) 400, 500, 600, 660, 700 CPU 32-/64-bit Ethernet MAC 10/100 Rating Automotive Operating temperature range (°C) -40 to 125
DSP type 1 C64x DSP (max) (MHz) 400, 500, 600, 660, 700 CPU 32-/64-bit Ethernet MAC 10/100 Rating Automotive Operating temperature range (°C) -40 to 125
NFBGA (ZWT) 361 256 mm² 16 x 16
  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media Processor (DM6435)
    • 2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5280, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Video Processing Subsystem (VPSS), VPFE Only
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine
        • Resize Images From 1/4× to 4×
        • Separate Horizontal/Vertical Control
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-Bit-Wide Data)
        • NAND (8-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Multichannel Buffered Serial Port (McBSP)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • High-End CAN Controller (HECC)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-5Q/-4Q)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • Applications:
    • Digital Media
  • Networked Media Encode
  • Video Imaging

All trademarks are the property of their respective owners.

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media Processor (DM6435)
    • 2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5280, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Video Processing Subsystem (VPSS), VPFE Only
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine
        • Resize Images From 1/4× to 4×
        • Separate Horizontal/Vertical Control
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-Bit-Wide Data)
        • NAND (8-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Multichannel Buffered Serial Port (McBSP)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • High-End CAN Controller (HECC)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-5Q/-4Q)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • Applications:
    • Digital Media
  • Networked Media Encode
  • Video Imaging

All trademarks are the property of their respective owners.

The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a configurable video port (VPFE); a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6435 device includes a Video Processing Subsystem (VPSS) with a configurable video/imaging front-end input peripheral used for video capture.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with host processors.

The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a configurable video port (VPFE); a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6435 device includes a Video Processing Subsystem (VPSS) with a configurable video/imaging front-end input peripheral used for video capture.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with host processors.

The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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其他裝置和產品規格表

本產品規格表適用於 TMS320DM6435 和 TMS320DM6435Q

技術文件

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類型 標題 日期
* Data sheet TMS320DM6435 Digital Media Processor datasheet (Rev. C) 2008年 6月 6日
* Errata TMS320DM6437/35/33/31 DMP Silicon Errata (Revs. 1.3 1.2 1.1 & 1.0) (Rev. E) 2011年 8月 12日
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015年 8月 13日
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 2012年 8月 21日
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 2012年 8月 21日
Application note Using the TMS320DM643x Bootloader (Rev. E) 2012年 3月 23日
User guide TMS320C6000 Programmer's Guide (Rev. K) 2011年 7月 11日
User guide TMS320DM643x DMP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. E) 2011年 3月 25日
User guide TMS320DM643x DMP DDR2 Memory Controller User's Guide (Rev. C) 2011年 1月 12日
User guide TMS320DM643x DMP EMAC/MDIO User's Guide (Rev. C) 2010年 12月 23日
User guide TMS320DM643x DMP Video Processing Front End (VPFE) User's Guide (Rev. D) 2010年 8月 25日
User guide TMS320DM643x DMP Pulse-Width Modulator (PWM) User's Guide (Rev. B) 2010年 8月 5日
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 2010年 8月 3日
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010年 7月 30日
Application note TMS320DM643x Power Consumption Summary (Rev. C) 2010年 5月 10日
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 2010年 3月 18日
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 2010年 3月 18日
User guide TMS320DM643x DMP Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. C) 2009年 12月 16日
Application note Common Object File Format (COFF) 2009年 4月 15日
User guide TMS320DM643x DMP Asynchronous External Memory Interface (EMIF) UG (Rev. B) 2009年 2月 24日
User guide TMS320C64x+ DSP Cache User's Guide (Rev. B) 2009年 2月 11日
Application note 12Vin DM643x Power using Integrated-FET DC/DC Converters and LDO 2008年 10月 9日
Application note 5Vin DM643x Power using DC/DC Controllers and LDO 2008年 10月 9日
Application note 5Vin DM643x Power using Integrated-FET DC/DC Converters and LDO 2008年 10月 9日
Application note 5Vin DM643x Power using a PMIC (Multi-output DC/DC Converter) 2008年 10月 9日
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 2008年 8月 21日
Application note Understanding the Davinci Preview Engine (Rev. A) 2008年 7月 23日
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008年 7月 17日
Application note Understanding the Davinci Resizer (Rev. B) 2008年 7月 17日
User guide TMS320DM643x DMP Host Port Interface (HPI) User's Guide (Rev. D) 2008年 7月 16日
Application note Implementing DDR2 PCB Layout on the TMS320DM643x DMSoC (Rev. A) 2008年 6月 26日
Application note How to Use the EDMA3 Driver on a TMS320DM643x Device (Rev. A) 2008年 6月 16日
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 2008年 5月 15日
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 2008年 5月 15日
User guide TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 2008年 5月 5日
User guide TMS320DM643x DMP General-Purpose Input/Output (GPIO) User's Guide (Rev. B) 2008年 3月 18日
User guide TMS320DM643x DMP Multichannel Audio Serial Port (McASP) User's Guide (Rev. D) 2008年 3月 13日
User guide TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 2008年 3月 6日
User guide TMS320DM643x DMP Enhanced DMA (EDMA) Controller User's Guide (Rev. A) 2008年 3月 3日
User guide TMS320DM643x DMP DSP Subsystem Reference Guide (Rev. E) 2008年 2月 5日
Application note How to Use the VPBE and VPFE Driver on the TMS320DM643x Devices (Rev. A) 2007年 11月 14日
User guide TMS320DM643x DMP VLYNQ Port User's Guide (Rev. B) 2007年 9月 20日
User guide TMS320DM643x DMP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. C) 2007年 9月 17日
Application note TMS320DM643x Pin Multiplexing Utility 2007年 7月 6日
User guide TMS320DM643x DMP Peripherals Overview Reference Guide (Rev. A) 2007年 6月 25日
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007年 5月 20日
User guide TMS320DM643x DMP High-End CAN Controller (HECC) User's Guide (Rev. A) 2007年 5月 15日
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007年 4月 4日
Product overview DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) 2007年 2月 13日
More literature Overview of DaVinci™ TMS320DM643x Digital Media Portfolio (Rev. B) 2007年 2月 13日
Application note DaVinci Technology Background and Specifications (Rev. A) 2007年 1月 4日
User guide TMS320DM643x DMP 64-Bit Timer User's Guide 2006年 12月 18日
User guide TMS320C64x+ DSP Big-Endian Library Programmer's Reference 2006年 3月 10日
User guide TMS320C64x+ Image/Video Processing Library Programmer's Reference 2006年 3月 10日
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 2005年 10月 20日

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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比,XDS200 是兼具低成本與優異效能的完美平衡,可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE

XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現,支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意,序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板,並透過 USB2.0 高速 (480Mbps) (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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應用軟體及架構

TMDMFP — 多媒體框架產品 (MFP) - 轉碼器引擎、框架元件和 XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

使用指南: PDF
驅動程式或資料庫

AEC-AER Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
66AK2G12 高效能多核心 DSP+Arm - 1x Arm A15 核心、1x C66x DSP 核心
數位訊號處理器 (DSP)
DM505 適用視覺分析 15mm 封裝的 SoC SM320C6201-EP 增強型產品 C6201 定點 DSP SM320C6415-EP 增強型產品 C6415 定點 DSP SM320C6424-EP 強化型產品 C6424 定點 DSP SM320C6455-EP 強化型產品 C6455 定點 DSP SM320C6472-HIREL 高可靠性產品 6 核心 C6472 定點 DSP SM320C6678-HIREL 高可靠性產品高效能 8 核心 C6678 定點和浮點 DSP SM320C6701 軍用應用的單核 C67x 浮點 DSP - 高達 167MHz SM320C6701-EP 增強型產品 C6701 浮點 DSP SM320C6711D-EP 增強型產品 C6711D 浮點 DSP SM320C6712D-EP 增強型產品 C6712D DSP SM320C6713B-EP 強化型產品 C6713 浮點 DSP SM320C6727B 軍用級 C6727B 浮點 DSP SM320C6727B-EP 強化型產品 C6727 浮點 DSP SMJ320C6201B 軍用定點數位訊號處理器 SMJ320C6203 軍用級 C62x 定點 DSP - 陶瓷封裝 SMJ320C6701 軍用級 C67x 浮點 DSP - 陶瓷封裝 SMJ320C6701-SP 航太級 C6701 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 SMV320C6727B-SP 航太級 C6727B 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 TMS320C5517 低功耗 C55x 定點 DSP - 高達 200MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定點 DSP - 高達 100MHz TMS320C5533 低功耗 C55x 定點 DSP - 高達 100MHz、USB TMS320C5534 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面 TMS320C5535 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C6202B C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 定點數位訊號處理器 TMS320C6205 定點數位訊號處理器 TMS320C6211B C62x 定點 DSP - 高達 167MHz TMS320C6414 C64x 定點 DSP - 高達 720MHz、McBSP TMS320C6415 C64x 定點 DSP - 高達 720MHz、McBSP、PCI TMS320C6416 C64x 定點 DSP - 高達 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424Q C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6454 C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6457 通訊基礎設施數位訊號處理器 TMS320C6701 C67x 浮點 DSP - 高達 167MHz、McBSP TMS320C6711D C67x 浮點 DSP - 高達 250MHz、McBSP、32 位元 EMIFA TMS320C6712D C67x 浮點 DSP - 高達 150MHz、McBSP、16 位元 EMIFA TMS320C6720 C67x 浮點 DSP - 200MHz、McASP、16 位元 EMIFA TMS320C6722B C67x 浮點 DSP - 高達 250MHz、McASP、16 位元 EMIFA TMS320C6726B C67x 浮點 DSP - 高達 266MHz、McASP、16 位元 EMIFA TMS320C6727 C67x 浮點 DSP - 高達 250MHz、McASP、32 位元 EMIFA TMS320C6727B C67x 浮點 DSP - 高達 350MHz、McASP、32 位元 EMIFA TMS320C6743 低功耗 C674x 浮點 DSP- 375MHz TMS320C6745 低功耗 C674x 浮點 DSP- 456MHz,QFP TMS320C6747 低功耗 C674x 浮點 DSP- 456MHz,PBGA TMS320DM642Q 視訊/成像定點數位訊號處理器 TMS320DM6431Q 數位媒體處理器,高達 2400 MIPS、300 MHz 時脈速率 TMS320DM6435Q 數位媒體處理器,最高達 4800 MIPS、600 MHz 時脈速率、1 McASP、1 McBSP TMS320DM6437Q 數位媒體處理器,最高達 4800 MIPS、600 MHz 時脈速率、1 個 McASP、2 個 McBSP TMS320DM6441 DaVinci 數位媒體晶片系統 TMS320DM6467T 數位媒體晶片系統 TMS320DM647 數位媒體處理器
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FAXLIB FAX library (FAXLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
66AK2G12 高效能多核心 DSP+Arm - 1x Arm A15 核心、1x C66x DSP 核心
數位訊號處理器 (DSP)
DM505 適用視覺分析 15mm 封裝的 SoC SM320C6201-EP 增強型產品 C6201 定點 DSP SM320C6415-EP 增強型產品 C6415 定點 DSP SM320C6424-EP 強化型產品 C6424 定點 DSP SM320C6455-EP 強化型產品 C6455 定點 DSP SM320C6472-HIREL 高可靠性產品 6 核心 C6472 定點 DSP SM320C6678-HIREL 高可靠性產品高效能 8 核心 C6678 定點和浮點 DSP SM320C6701 軍用應用的單核 C67x 浮點 DSP - 高達 167MHz SM320C6701-EP 增強型產品 C6701 浮點 DSP SM320C6711D-EP 增強型產品 C6711D 浮點 DSP SM320C6712D-EP 增強型產品 C6712D DSP SM320C6713B-EP 強化型產品 C6713 浮點 DSP SM320C6727B 軍用級 C6727B 浮點 DSP SM320C6727B-EP 強化型產品 C6727 浮點 DSP SMJ320C6201B 軍用定點數位訊號處理器 SMJ320C6203 軍用級 C62x 定點 DSP - 陶瓷封裝 SMJ320C6701 軍用級 C67x 浮點 DSP - 陶瓷封裝 SMJ320C6701-SP 航太級 C6701 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 SMV320C6727B-SP 航太級 C6727B 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 TMS320C5517 低功耗 C55x 定點 DSP - 高達 200MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定點 DSP - 高達 100MHz TMS320C5533 低功耗 C55x 定點 DSP - 高達 100MHz、USB TMS320C5534 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面 TMS320C5535 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C6202B C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 定點數位訊號處理器 TMS320C6205 定點數位訊號處理器 TMS320C6211B C62x 定點 DSP - 高達 167MHz TMS320C6414 C64x 定點 DSP - 高達 720MHz、McBSP TMS320C6415 C64x 定點 DSP - 高達 720MHz、McBSP、PCI TMS320C6416 C64x 定點 DSP - 高達 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424Q C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6454 C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6457 通訊基礎設施數位訊號處理器 TMS320C6701 C67x 浮點 DSP - 高達 167MHz、McBSP TMS320C6711D C67x 浮點 DSP - 高達 250MHz、McBSP、32 位元 EMIFA TMS320C6712D C67x 浮點 DSP - 高達 150MHz、McBSP、16 位元 EMIFA TMS320C6720 C67x 浮點 DSP - 200MHz、McASP、16 位元 EMIFA TMS320C6722B C67x 浮點 DSP - 高達 250MHz、McASP、16 位元 EMIFA TMS320C6726B C67x 浮點 DSP - 高達 266MHz、McASP、16 位元 EMIFA TMS320C6727 C67x 浮點 DSP - 高達 250MHz、McASP、32 位元 EMIFA TMS320C6727B C67x 浮點 DSP - 高達 350MHz、McASP、32 位元 EMIFA TMS320C6743 低功耗 C674x 浮點 DSP- 375MHz TMS320C6745 低功耗 C674x 浮點 DSP- 456MHz,QFP TMS320C6747 低功耗 C674x 浮點 DSP- 456MHz,PBGA TMS320DM642Q 視訊/成像定點數位訊號處理器 TMS320DM6431Q 數位媒體處理器,高達 2400 MIPS、300 MHz 時脈速率 TMS320DM6435Q 數位媒體處理器,最高達 4800 MIPS、600 MHz 時脈速率、1 McASP、1 McBSP TMS320DM6437Q 數位媒體處理器,最高達 4800 MIPS、600 MHz 時脈速率、1 個 McASP、2 個 McBSP TMS320DM6441 DaVinci 數位媒體晶片系統 TMS320DM6467T 數位媒體晶片系統 TMS320DM647 數位媒體處理器
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驅動程式或資料庫

SPRC122 C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

支援產品和硬體

支援產品和硬體

產品
數位訊號處理器 (DSP)
SM320C6201-EP 增強型產品 C6201 定點 DSP SM320C6455-EP 強化型產品 C6455 定點 DSP SMJ320C6201B 軍用定點數位訊號處理器 SMJ320C6203 軍用級 C62x 定點 DSP - 陶瓷封裝 TMS320C6202B C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 定點數位訊號處理器 TMS320C6205 定點數位訊號處理器 TMS320C6211B C62x 定點 DSP - 高達 167MHz TMS320C6412 C64x 定點 DSP - 高達 720MHz、McBSP、McASP、I2cC、乙太網路 TMS320C6414 C64x 定點 DSP - 高達 720MHz、McBSP TMS320C6414T C64x 定點 DSP - 高達 1GHz、McBSP TMS320C6415 C64x 定點 DSP - 高達 720MHz、McBSP、PCI TMS320C6415T C64x 定點 DSP - 高達 850MHz、McBSP、PCI TMS320C6416 C64x 定點 DSP - 高達 720MHz、McBSP、PCI、VCP/TCP TMS320C6416T C64x 定點 DSP - 高達 850MHz、McBSP、PCI、VCP/TCP TMS320C6421 C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2、SDRAM TMS320C6421Q C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424 C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2、SDRAM TMS320C6424Q C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6452 C64x+ 定點 DSP - 高達 900MHz、1Gbps 乙太網路 TMS320C6454 C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6455 C64x+ 定點 DSP 最高 1.2GHz、64 位元 EMIFA、32 與 16 位元 DDR2、1Gbps 乙太網路 TMS320C6457 通訊基礎設施數位訊號處理器 TMS320C6474 多核數位訊號處理器 TMS320DM640 視訊/成像定點數位訊號處理器 TMS320DM641 視訊/成像定點數位訊號處理器 TMS320DM642 視訊/成像定點數位訊號處理器 TMS320DM642Q 視訊/成像定點數位訊號處理器 TMS320DM6431 數位媒體處理器 TMS320DM6431Q 數位媒體處理器,高達 2400 MIPS、300 MHz 時脈速率 TMS320DM6433 數位媒體處理器 TMS320DM6435 數位媒體處理器 TMS320DM6435Q 數位媒體處理器,最高達 4800 MIPS、600 MHz 時脈速率、1 McASP、1 McBSP TMS320DM6437 數位媒體處理器 TMS320DM6437Q 數位媒體處理器,最高達 4800 MIPS、600 MHz 時脈速率、1 個 McASP、2 個 McBSP TMS320DM6441 DaVinci 數位媒體晶片系統 TMS320DM6443 DaVinci 數位媒體晶片系統 TMS320DM6446 DaVinci 數位媒體晶片系統
驅動程式或資料庫

VOLIB Voice library (VoLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
66AK2G12 高效能多核心 DSP+Arm - 1x Arm A15 核心、1x C66x DSP 核心
數位訊號處理器 (DSP)
DM505 適用視覺分析 15mm 封裝的 SoC SM320C6201-EP 增強型產品 C6201 定點 DSP SM320C6415-EP 增強型產品 C6415 定點 DSP SM320C6424-EP 強化型產品 C6424 定點 DSP SM320C6455-EP 強化型產品 C6455 定點 DSP SM320C6472-HIREL 高可靠性產品 6 核心 C6472 定點 DSP SM320C6678-HIREL 高可靠性產品高效能 8 核心 C6678 定點和浮點 DSP SM320C6701 軍用應用的單核 C67x 浮點 DSP - 高達 167MHz SM320C6701-EP 增強型產品 C6701 浮點 DSP SM320C6711D-EP 增強型產品 C6711D 浮點 DSP SM320C6712D-EP 增強型產品 C6712D DSP SM320C6713B-EP 強化型產品 C6713 浮點 DSP SM320C6727B 軍用級 C6727B 浮點 DSP SM320C6727B-EP 強化型產品 C6727 浮點 DSP SMJ320C6201B 軍用定點數位訊號處理器 SMJ320C6203 軍用級 C62x 定點 DSP - 陶瓷封裝 SMJ320C6701 軍用級 C67x 浮點 DSP - 陶瓷封裝 SMJ320C6701-SP 航太級 C6701 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 SMV320C6727B-SP 航太級 C6727B 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 TMS320C5517 低功耗 C55x 定點 DSP - 高達 200MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定點 DSP - 高達 100MHz TMS320C5533 低功耗 C55x 定點 DSP - 高達 100MHz、USB TMS320C5534 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面 TMS320C5535 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C6202B C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 定點數位訊號處理器 TMS320C6205 定點數位訊號處理器 TMS320C6211B C62x 定點 DSP - 高達 167MHz TMS320C6414 C64x 定點 DSP - 高達 720MHz、McBSP TMS320C6415 C64x 定點 DSP - 高達 720MHz、McBSP、PCI TMS320C6416 C64x 定點 DSP - 高達 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424Q C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6454 C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6457 通訊基礎設施數位訊號處理器 TMS320C6701 C67x 浮點 DSP - 高達 167MHz、McBSP TMS320C6711D C67x 浮點 DSP - 高達 250MHz、McBSP、32 位元 EMIFA TMS320C6712D C67x 浮點 DSP - 高達 150MHz、McBSP、16 位元 EMIFA TMS320C6720 C67x 浮點 DSP - 200MHz、McASP、16 位元 EMIFA TMS320C6722B C67x 浮點 DSP - 高達 250MHz、McASP、16 位元 EMIFA TMS320C6726B C67x 浮點 DSP - 高達 266MHz、McASP、16 位元 EMIFA TMS320C6727 C67x 浮點 DSP - 高達 250MHz、McASP、32 位元 EMIFA TMS320C6727B C67x 浮點 DSP - 高達 350MHz、McASP、32 位元 EMIFA TMS320C6743 低功耗 C674x 浮點 DSP- 375MHz TMS320C6745 低功耗 C674x 浮點 DSP- 456MHz,QFP TMS320C6747 低功耗 C674x 浮點 DSP- 456MHz,PBGA TMS320DM642Q 視訊/成像定點數位訊號處理器 TMS320DM6431Q 數位媒體處理器,高達 2400 MIPS、300 MHz 時脈速率 TMS320DM6435Q 數位媒體處理器,最高達 4800 MIPS、600 MHz 時脈速率、1 McASP、1 McBSP TMS320DM6437Q 數位媒體處理器,最高達 4800 MIPS、600 MHz 時脈速率、1 個 McASP、2 個 McBSP TMS320DM6441 DaVinci 數位媒體晶片系統 TMS320DM6467T 數位媒體晶片系統 TMS320DM647 數位媒體處理器
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軟體轉碼器

TMDXDAISXDM — eXpressDSP 演算法標準 – xDAIS 開發套件和 xDM

xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

使用指南: PDF
模擬型號

DM6435 ZDU BSDL Model (Rev. A)

SPRM227A.ZIP (10 KB) - BSDL Model
模擬型號

DM6435 ZDU IBIS Model (Rev. B)

SPRM233B.ZIP (267 KB) - IBIS Model
模擬型號

DM6435 ZWT BSDL Model (Rev. A)

SPRM226A.ZIP (10 KB) - BSDL Model
模擬型號

DM6435 ZWT IBIS Model (Rev. B)

SPRM232B.ZIP (267 KB) - IBIS Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (ZWT) 361 Ultra Librarian

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  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

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