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Arm 式處理器

66AK2G12

現行

高效能多核心 DSP+Arm - 1x Arm A15 核心、1x C66x DSP 核心

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66AK2G12

現行
產品規格表 立即訂購

產品詳細資料

Arm CPU 1 Arm Cortex-A15 Arm (max) (MHz) 600, 1000 Coprocessors C66x DSP CPU 32-bit Display type 1 LCD Ethernet MAC 1-Port 1Gb, 4-Port 10/100 PRU EMAC PCIe 1 PCIe Gen 2 Hardware accelerators PRU-ICSS, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Memory protection, Secure boot Rating Catalog Operating temperature range (°C) -40 to 125
Arm CPU 1 Arm Cortex-A15 Arm (max) (MHz) 600, 1000 Coprocessors C66x DSP CPU 32-bit Display type 1 LCD Ethernet MAC 1-Port 1Gb, 4-Port 10/100 PRU EMAC PCIe 1 PCIe Gen 2 Hardware accelerators PRU-ICSS, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Memory protection, Secure boot Rating Catalog Operating temperature range (°C) -40 to 125
FCCSP (ABY) 625 441 mm² 21 x 21
  • Processor cores:
  • Arm® Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000 MHz
    • Supports full Implementation of Armv7-A architecture instruction set
    • Integrated SIMDv2 (Arm® Neon™ Technology) and VFPv4 (Vector Floating Point)
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 512KB of L2 memory
    • Error Correction Code (ECC) protection for L1 data memory ECC for L2 memory
    • Parity protection for L1 program memory
    • Global Timebase Counter (GTC)
      • 64-Bit free-running counter that provides timebase for Arm A15 internal timers
      • Compliant to Armv7 MPCore Architecture for Generic Timers
  • C66x fixed- and floating-point VLIW DSP subsystem at up to 1000 MHz
    • Fully object-code compatible With C67x+ and C64x+ cores
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 1024KB of L2 configurable as L2 RAM or cache
    • Error detection for L1 program memory
    • ECC for L1 data memory
    • ECC for L2 data memory
  • Industrial subsystem:
  • Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), each supports:
    • Two Programmable Real-Time Units (PRUs) with enhanced multiplier and accumulator, each PRU supports:
      • 16KB of program memory With ECC
      • 8KB of data memory With ECC
      • CRC32 and CRC16 hardware accelerator
      • 20 × enhanced GPIO
      • Serial Capture Unit (SCU), supporting direct connection, 16-bit parallel capture, 28-bit shift, MII_RT, EnDat 2.2 protocol and Sigma-Delta demodulation
      • Scratch pad and XFR direct connect
    • 64KB of general-purpose memory With ECC
    • One Ethernet MII_RT module with two MII ports configurable for connection with each PRU; supports multiple industrial communication protocols
    • Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions
    • Built-In Universal Asynchronous Receiver and Transmitter (UART) 16550, with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS®
    • Built-In industrial Ethernet 64-Bit timer
    • Built-In enhanced capture module (eCAP)
  • Memory subsystem:
  • Multicore Shared Memory Controller (MSMC) with 1024KB of shared L2 RAM
    • Provides high-performance interconnect to internal shared SRAM and DDR EMIF for both Arm A15 and C66x Access
    • Supports Arm I/O coherency where Arm A15 is cache coherent to other system masters accessing the MSMC-SRAM or DDR EMIF
    • Supports ECC on SRAM
  • Up to 36-Bit DDR External Memory Interface (EMIF)
    • Supports DDR3L at up to 1066 MT/s
    • Supports 4-GB memory address range
    • Supports 32-Bit SDRAM data bus with 4-bit ECC
    • Supports 16-Bit and 32-Bit SDRAM data bus without ECC
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit asynchronous memory interface with up to four chip selects
    • Supports NOR, Muxed-NOR, SRAM
    • Supports general-purpose memory-port expansion with the following modes:
      • Asynchronous read and write access
      • Asynchronous read page access (4-, 8-, 16-Word16)
      • Synchronous read and write access
      • Synchronous read burst access without wrap capability (4-, 8-, 16-Word16)
  • Network Subsystem (NSS):
  • Ethernet MAC (EMAC) subsystem
    • One-port Gigabit Ethernet: RMII, MII, RGMII
    • Supports 10-, 100-, 1000-Mbps full duplex
    • Supports 10-, 100-Mbps half duplex
    • Supports Ethernet Audio Video Bridging (eAVB)
    • Maximum frame size 2016 Bytes (2020 Bytes with VLAN)
    • Eight priority level QOS support (802.1p)
    • IEEE 1588v2 (2008 Annex D, Annex E, and
      Annex F) to facilitate Audio Video Bridging 802.1AS Precision Time Protocol (PTP)
    • CPTS module with timestamping support for IEEE 1588v2
    • DSCP priority mapping (IPv4 and IPv6)
    • MDIO module for PHY management
    • Enhanced statistics collection
  • Navigator Subsystem (NAVSS)
    • Built-In packet DMA controller for optimized network processing
    • Built-In Queue Manager (QM) for optimized network processing
      • Supports up to 128 queues
      • 2048 buffers supported in internal queue RAM
  • Crypto Engine (SA) supports:
    • Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations
    • Block data encryption supported through hardware cores
      • AES with 128-, 192-, and 256-Bit Key supports
      • DES and 3DES with 1, 2, or 3 Different Key support
    • Programmable Mode Control Engine (MCE)
    • Public Key Accelerator (PKA) with elliptic curve cryptography
    • Elliptic Curve Diffie–Hellman (ECDH) based key exchange and digital signature (ECDSA) applications
    • Authentication for SHA1, MD5, SHA2-224 and SHA2-256
    • Keyed HMAC operation through hardware core
    • True Random Number Generator (TRNG)
  • Display Subsystem:
  • Supports one video pipe with in-loop scaling, color space
  • Conversion and background color overlay
  • Input data format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
  • Supported display interfaces:
    • MIPI® DPI 2.0 parallel interface
    • RFBI (MIPI-DBI 2.0) up to QVGA at 30fps
    • BT.656 4:2:2
    • BT.1120 4:2:2 up to 1920 × 1080 at 30fps
  • In-loop scaling capability
  • LCD interface supports:
    • Active Matrix (TFT)
    • Passive Matrix (STN)
    • Grayscale
    • TDM
    • AC Bias Control
    • Dither
    • CPR
  • Asynchronous Audio Sample Rate Converter (ASRC)
  • High performance asynchronous sample rate converter with 140 dB Signal-to-Noise (SNR)
  • Up to 8 stereo streams (16 audio channels)
  • Automatically sensing / detection of input sample frequencies
  • Attenuation of sampling clock jitter
  • 16-, 18-, 20-, 24-Bit data input/output
  • Audio sample rates from 8 kHz to 216 kHz
  • Input/output sampling ratios from 16:1 to 1:16
  • Group mode, where multiple ASRC blocks use the same timing loop for input or output
  • Linear phase FIR filter
  • Controllable soft mute
  • Independent clock generator, and rate and stamp generator, for each input and output clock zone
  • Separate DMA events for input and output, for each channel and group
  • High-speed serial interfaces:
  • PCI Express® 2.0 port with integrated PHY:
    • Single lane Gen2-compliant port
    • Root Complex (RC) and End Point (EP) modes
  • Up to two USB 2.0 High-Speed dual-role ports with Integrated PHYs, support:
    • Dual-role-device (DRD) Capability with:
      • USB 2.0 peripheral (or device) at
        HS (480Mbps) and FS (12Mbps) speeds
      • USB 2.0 host at HS (480Mbps),
        FS (12Mbps), and LS (1.5Mbps) speeds
      • USB 2.0 static peripheral and static host operations
    • xHCI controller with the following features:
      • Compatible to the xHCI specification (revision 1.1) in host mode
      • All modes of transfer (control, bulk, interrupt, and isochronous)
      • 15 transmit (TX), 15 receive (RX) endpoints (EPs), and one bidirectional endpoint (EP0)
  • Flash media interfaces:
  • QSPI™ with XIP and up to four chip selects, supports:
    • Memory-mapped direct mode of operation for performing FLASH data transfers and executing code from FLASH memory (XIP)
    • Supports up to 96 MHz
    • Internal SRAM buffer with ECC
    • High speed read data capture mechanism
  • Two Multimedia Card (MMC) and Secure Digital (SD) ports
    • Supports JEDEC JESD84 v4.5-A441 and SD3.0 physical layer with SDA3.00 standards
    • MMC0 supports 3.3-V I/O for:
      • SD DS and HS mode
      • eMMC mode HS-SDR
        up to 48 MHz
    • MMC1 supports 1.8-V I/O modes for eMMC, including HS-SDR and DDR at up to 48 MHz with 4- and 8-Bit bus width
  • Audio peripherals:
  • Three Multichannel Audio Serial Port (McASP) peripherals
    • Transmit and receive clocks up to 50 MHz
    • Two independent clock zones and independent transmit and receive clocks per McASP
    • Up to 16-, 10-, 6-serial data pins for McASP0, McASP1, and McASP2, respectively
    • Supports TDM, I2S, and similar formats
    • Supports DIT mode
    • Built-In FIFO buffers for optimized system traffic
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and receive clocks up to 50 MHz
    • Two clock zones and two serial-data pins
    • Supports TDM, I2S, and similar formats
  • Real-time control interfaces:
  • Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter supports:
    • Dedicated 16-Bit Time-Base with Period and Frequency Control
    • Two independent PWM outputs with single edge operation
    • Two independent PWM outputs with dual-edge symmetric operation
    • One independent PWM output with dual-edge asymmetric operation
  • Two 32-Bit Enhanced Capture Modules (eCAP):
    • Supports one capture input or one auxiliary PWM output configuration options
    • 4-Event time-stamp registers (Each 32-Bits)
    • Interrupt on either of the four events
  • Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), each supports:
    • Quadrature decoding
    • Position counter and control unit for position measurement
    • Unit time base for speed and frequency measurement
  • General connectivity:
  • Two Controller Area Network (CAN) Ports
    • Supports CAN v2.0 Part A, B (ISO 11898-1) protocol
    • Bit rates up to 1 Mbps
    • Dual clock source
    • ECC protection for message RAM
  • One Media Local Bus (MLB)
    • Supports both 3-pin (up to MOST50, 1024 × Fs) and 6-pin (up to MOST150, 2048 × Fs) versions of MediaLB® Physical layer specification v4.2
    • Supports all types of data transfer over 64 logical channels (synchronous stream, isochronous, asynchronous packet, control message)
    • Supports 3-wire MOST 150 protocol
  • Three Inter-Integrated Circuit (I2C) interfaces, each supports:
    • Standard (up to 100 kHz) and
      Fast (up to 400 kHz) modes
    • 7-Bit addressing mode
    • Supports EEPROM size up to 4Mbit
  • Four Serial Peripheral Interfaces (SPI), each supports:
    • Operates at up to 50 MHz in master mode and 25 MHz in slave mode
    • Two chip selects
  • Three UART interfaces
    • All UARTs are 16C750-compatible and operate at up to 3M baud
    • UART0 supports 8 pins with full modem control, with DSR, DTR, DCD, and RI signals
    • UART1 and UART2 are 4-pin interfaces
  • General-Purpose I/O (GPIO)
    • Up to 212 GPIOs muxed with other interfaces
    • Can be configured as interrupt pins
  • Timers and miscellaneous modules:
  • Seven 64-Bit timers:
    • Two 64-Bit timers dedicated to Arm A15 and DSP cores (one timer per core)
      • Watchdog and General-Purpose (GP)
    • Four 64-Bit timers are shared for general purposes
    • Each 64-Bit timer can be configured as two individual 32-Bit timers
    • One 64-Bit timer dedicated for PMMC
    • Two timers input/output pin pairs
  • Interprocessor communication with:
    • Message manager to facilitate multiprocessor access to the PMMC:
      • Provides hardware acceleration for pushing and popping messages to/from logical queues
      • Supports up to 64 queues and 128 messages
    • Semaphore module with up to 64 independent semaphores and 16 masters (device cores)
  • EDMA with 128 (2 × 64) channels and
    1024 (2 × 512) PaRAM entries
  • Keystone II System on Chip (SoC) architecture:
  • Security
    • Supports General-Purpose (GP) and High-Secure (HS) devices
    • Supports secure boot
    • Supports customer secondary keys
    • 4KB of One-Time Programmable (OTP) ROM for customer keys
  • Power management
    • Integrated Power Management Microcontroller (PMMC) technology
  • Supports primary boot from UART, I2C, SPI, GPMC, SD or eMMC, USB device firmware upgrade v1.1, PCIe®, and Ethernet interfaces
  • Keystone II debug architecture with integrated Arm CoreSight™ support and trace capability
  • Operating Temperature (TJ):
  • –40°C to 125°C (Industrial Extended)
  • –40°C to 105°C (Extended)
  • 0°C to 90°C (Commercial)
  • Processor cores:
  • Arm® Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000 MHz
    • Supports full Implementation of Armv7-A architecture instruction set
    • Integrated SIMDv2 (Arm® Neon™ Technology) and VFPv4 (Vector Floating Point)
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 512KB of L2 memory
    • Error Correction Code (ECC) protection for L1 data memory ECC for L2 memory
    • Parity protection for L1 program memory
    • Global Timebase Counter (GTC)
      • 64-Bit free-running counter that provides timebase for Arm A15 internal timers
      • Compliant to Armv7 MPCore Architecture for Generic Timers
  • C66x fixed- and floating-point VLIW DSP subsystem at up to 1000 MHz
    • Fully object-code compatible With C67x+ and C64x+ cores
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 1024KB of L2 configurable as L2 RAM or cache
    • Error detection for L1 program memory
    • ECC for L1 data memory
    • ECC for L2 data memory
  • Industrial subsystem:
  • Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), each supports:
    • Two Programmable Real-Time Units (PRUs) with enhanced multiplier and accumulator, each PRU supports:
      • 16KB of program memory With ECC
      • 8KB of data memory With ECC
      • CRC32 and CRC16 hardware accelerator
      • 20 × enhanced GPIO
      • Serial Capture Unit (SCU), supporting direct connection, 16-bit parallel capture, 28-bit shift, MII_RT, EnDat 2.2 protocol and Sigma-Delta demodulation
      • Scratch pad and XFR direct connect
    • 64KB of general-purpose memory With ECC
    • One Ethernet MII_RT module with two MII ports configurable for connection with each PRU; supports multiple industrial communication protocols
    • Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions
    • Built-In Universal Asynchronous Receiver and Transmitter (UART) 16550, with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS®
    • Built-In industrial Ethernet 64-Bit timer
    • Built-In enhanced capture module (eCAP)
  • Memory subsystem:
  • Multicore Shared Memory Controller (MSMC) with 1024KB of shared L2 RAM
    • Provides high-performance interconnect to internal shared SRAM and DDR EMIF for both Arm A15 and C66x Access
    • Supports Arm I/O coherency where Arm A15 is cache coherent to other system masters accessing the MSMC-SRAM or DDR EMIF
    • Supports ECC on SRAM
  • Up to 36-Bit DDR External Memory Interface (EMIF)
    • Supports DDR3L at up to 1066 MT/s
    • Supports 4-GB memory address range
    • Supports 32-Bit SDRAM data bus with 4-bit ECC
    • Supports 16-Bit and 32-Bit SDRAM data bus without ECC
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit asynchronous memory interface with up to four chip selects
    • Supports NOR, Muxed-NOR, SRAM
    • Supports general-purpose memory-port expansion with the following modes:
      • Asynchronous read and write access
      • Asynchronous read page access (4-, 8-, 16-Word16)
      • Synchronous read and write access
      • Synchronous read burst access without wrap capability (4-, 8-, 16-Word16)
  • Network Subsystem (NSS):
  • Ethernet MAC (EMAC) subsystem
    • One-port Gigabit Ethernet: RMII, MII, RGMII
    • Supports 10-, 100-, 1000-Mbps full duplex
    • Supports 10-, 100-Mbps half duplex
    • Supports Ethernet Audio Video Bridging (eAVB)
    • Maximum frame size 2016 Bytes (2020 Bytes with VLAN)
    • Eight priority level QOS support (802.1p)
    • IEEE 1588v2 (2008 Annex D, Annex E, and
      Annex F) to facilitate Audio Video Bridging 802.1AS Precision Time Protocol (PTP)
    • CPTS module with timestamping support for IEEE 1588v2
    • DSCP priority mapping (IPv4 and IPv6)
    • MDIO module for PHY management
    • Enhanced statistics collection
  • Navigator Subsystem (NAVSS)
    • Built-In packet DMA controller for optimized network processing
    • Built-In Queue Manager (QM) for optimized network processing
      • Supports up to 128 queues
      • 2048 buffers supported in internal queue RAM
  • Crypto Engine (SA) supports:
    • Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations
    • Block data encryption supported through hardware cores
      • AES with 128-, 192-, and 256-Bit Key supports
      • DES and 3DES with 1, 2, or 3 Different Key support
    • Programmable Mode Control Engine (MCE)
    • Public Key Accelerator (PKA) with elliptic curve cryptography
    • Elliptic Curve Diffie–Hellman (ECDH) based key exchange and digital signature (ECDSA) applications
    • Authentication for SHA1, MD5, SHA2-224 and SHA2-256
    • Keyed HMAC operation through hardware core
    • True Random Number Generator (TRNG)
  • Display Subsystem:
  • Supports one video pipe with in-loop scaling, color space
  • Conversion and background color overlay
  • Input data format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
  • Supported display interfaces:
    • MIPI® DPI 2.0 parallel interface
    • RFBI (MIPI-DBI 2.0) up to QVGA at 30fps
    • BT.656 4:2:2
    • BT.1120 4:2:2 up to 1920 × 1080 at 30fps
  • In-loop scaling capability
  • LCD interface supports:
    • Active Matrix (TFT)
    • Passive Matrix (STN)
    • Grayscale
    • TDM
    • AC Bias Control
    • Dither
    • CPR
  • Asynchronous Audio Sample Rate Converter (ASRC)
  • High performance asynchronous sample rate converter with 140 dB Signal-to-Noise (SNR)
  • Up to 8 stereo streams (16 audio channels)
  • Automatically sensing / detection of input sample frequencies
  • Attenuation of sampling clock jitter
  • 16-, 18-, 20-, 24-Bit data input/output
  • Audio sample rates from 8 kHz to 216 kHz
  • Input/output sampling ratios from 16:1 to 1:16
  • Group mode, where multiple ASRC blocks use the same timing loop for input or output
  • Linear phase FIR filter
  • Controllable soft mute
  • Independent clock generator, and rate and stamp generator, for each input and output clock zone
  • Separate DMA events for input and output, for each channel and group
  • High-speed serial interfaces:
  • PCI Express® 2.0 port with integrated PHY:
    • Single lane Gen2-compliant port
    • Root Complex (RC) and End Point (EP) modes
  • Up to two USB 2.0 High-Speed dual-role ports with Integrated PHYs, support:
    • Dual-role-device (DRD) Capability with:
      • USB 2.0 peripheral (or device) at
        HS (480Mbps) and FS (12Mbps) speeds
      • USB 2.0 host at HS (480Mbps),
        FS (12Mbps), and LS (1.5Mbps) speeds
      • USB 2.0 static peripheral and static host operations
    • xHCI controller with the following features:
      • Compatible to the xHCI specification (revision 1.1) in host mode
      • All modes of transfer (control, bulk, interrupt, and isochronous)
      • 15 transmit (TX), 15 receive (RX) endpoints (EPs), and one bidirectional endpoint (EP0)
  • Flash media interfaces:
  • QSPI™ with XIP and up to four chip selects, supports:
    • Memory-mapped direct mode of operation for performing FLASH data transfers and executing code from FLASH memory (XIP)
    • Supports up to 96 MHz
    • Internal SRAM buffer with ECC
    • High speed read data capture mechanism
  • Two Multimedia Card (MMC) and Secure Digital (SD) ports
    • Supports JEDEC JESD84 v4.5-A441 and SD3.0 physical layer with SDA3.00 standards
    • MMC0 supports 3.3-V I/O for:
      • SD DS and HS mode
      • eMMC mode HS-SDR
        up to 48 MHz
    • MMC1 supports 1.8-V I/O modes for eMMC, including HS-SDR and DDR at up to 48 MHz with 4- and 8-Bit bus width
  • Audio peripherals:
  • Three Multichannel Audio Serial Port (McASP) peripherals
    • Transmit and receive clocks up to 50 MHz
    • Two independent clock zones and independent transmit and receive clocks per McASP
    • Up to 16-, 10-, 6-serial data pins for McASP0, McASP1, and McASP2, respectively
    • Supports TDM, I2S, and similar formats
    • Supports DIT mode
    • Built-In FIFO buffers for optimized system traffic
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and receive clocks up to 50 MHz
    • Two clock zones and two serial-data pins
    • Supports TDM, I2S, and similar formats
  • Real-time control interfaces:
  • Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter supports:
    • Dedicated 16-Bit Time-Base with Period and Frequency Control
    • Two independent PWM outputs with single edge operation
    • Two independent PWM outputs with dual-edge symmetric operation
    • One independent PWM output with dual-edge asymmetric operation
  • Two 32-Bit Enhanced Capture Modules (eCAP):
    • Supports one capture input or one auxiliary PWM output configuration options
    • 4-Event time-stamp registers (Each 32-Bits)
    • Interrupt on either of the four events
  • Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), each supports:
    • Quadrature decoding
    • Position counter and control unit for position measurement
    • Unit time base for speed and frequency measurement
  • General connectivity:
  • Two Controller Area Network (CAN) Ports
    • Supports CAN v2.0 Part A, B (ISO 11898-1) protocol
    • Bit rates up to 1 Mbps
    • Dual clock source
    • ECC protection for message RAM
  • One Media Local Bus (MLB)
    • Supports both 3-pin (up to MOST50, 1024 × Fs) and 6-pin (up to MOST150, 2048 × Fs) versions of MediaLB® Physical layer specification v4.2
    • Supports all types of data transfer over 64 logical channels (synchronous stream, isochronous, asynchronous packet, control message)
    • Supports 3-wire MOST 150 protocol
  • Three Inter-Integrated Circuit (I2C) interfaces, each supports:
    • Standard (up to 100 kHz) and
      Fast (up to 400 kHz) modes
    • 7-Bit addressing mode
    • Supports EEPROM size up to 4Mbit
  • Four Serial Peripheral Interfaces (SPI), each supports:
    • Operates at up to 50 MHz in master mode and 25 MHz in slave mode
    • Two chip selects
  • Three UART interfaces
    • All UARTs are 16C750-compatible and operate at up to 3M baud
    • UART0 supports 8 pins with full modem control, with DSR, DTR, DCD, and RI signals
    • UART1 and UART2 are 4-pin interfaces
  • General-Purpose I/O (GPIO)
    • Up to 212 GPIOs muxed with other interfaces
    • Can be configured as interrupt pins
  • Timers and miscellaneous modules:
  • Seven 64-Bit timers:
    • Two 64-Bit timers dedicated to Arm A15 and DSP cores (one timer per core)
      • Watchdog and General-Purpose (GP)
    • Four 64-Bit timers are shared for general purposes
    • Each 64-Bit timer can be configured as two individual 32-Bit timers
    • One 64-Bit timer dedicated for PMMC
    • Two timers input/output pin pairs
  • Interprocessor communication with:
    • Message manager to facilitate multiprocessor access to the PMMC:
      • Provides hardware acceleration for pushing and popping messages to/from logical queues
      • Supports up to 64 queues and 128 messages
    • Semaphore module with up to 64 independent semaphores and 16 masters (device cores)
  • EDMA with 128 (2 × 64) channels and
    1024 (2 × 512) PaRAM entries
  • Keystone II System on Chip (SoC) architecture:
  • Security
    • Supports General-Purpose (GP) and High-Secure (HS) devices
    • Supports secure boot
    • Supports customer secondary keys
    • 4KB of One-Time Programmable (OTP) ROM for customer keys
  • Power management
    • Integrated Power Management Microcontroller (PMMC) technology
  • Supports primary boot from UART, I2C, SPI, GPMC, SD or eMMC, USB device firmware upgrade v1.1, PCIe®, and Ethernet interfaces
  • Keystone II debug architecture with integrated Arm CoreSight™ support and trace capability
  • Operating Temperature (TJ):
  • –40°C to 125°C (Industrial Extended)
  • –40°C to 105°C (Extended)
  • 0°C to 90°C (Commercial)

66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.

Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.

The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.

Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.

Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.

66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.

Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.

The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.

Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.

Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.
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類型 標題 日期
* Data sheet 66AK2G1x Multicore DSP+Arm KeyStone II System-on-Chip (SoC) datasheet (Rev. F) PDF | HTML 2019年 12月 10日
* Errata 66AK2G1x Errata (Rev. B) 2018年 6月 20日
* User guide 66AK2Gx Multicore DSP + ARM Keystone II System-on-Chip (SOC) TRM (Rev. I) 2019年 4月 18日
Application note Industrial Communication Protocols Supported on Sitara™ Processors (Rev. E) PDF | HTML 2024年 5月 10日
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
Application note PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022年 10月 11日
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022年 7月 7日
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 2021年 6月 25日
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021年 5月 19日
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019年 6月 11日
Application note KeyStone II DDR3 interface bring-up 2019年 3月 7日
White paper Designing professional audio mixers for every scenario 2018年 6月 28日
Design guide DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx-Based Systems (Rev. B) 2018年 6月 12日
Application note 66AK2G1x: EVMK2GX General-Purpose EVM Power Distribution Network Analysis 2018年 3月 14日
User guide PRU Assembly Instruction User Guide 2018年 2月 16日
Application note 66AK2G12 Power Consumption Summary 2018年 2月 9日
Application note 66AK2G12 Power Estimation Tool 2018年 1月 19日
User guide TPS65911A User’s Guide for 66AK2G12 Processor (Rev. A) 2017年 12月 18日
User guide 66AK2Gx Hardware Design Guide (Rev. A) 2017年 11月 14日
User guide 66AK2Gx BGA Escape Routing Stackup (Rev. A) 2017年 11月 14日
Application note 66AK2Gx Schematic Checklist (Rev. A) 2017年 11月 14日
User guide K2G General Purpose Evaluation Module (EVMK2G) TRM (Rev. A) 2017年 9月 20日
White paper Designing Embedded Systems for High Reliability With 66AK2Gx (Rev. A) 2017年 8月 28日
White paper Getting personal with the 66AK2Gx SoC (Rev. A) 2017年 8月 2日
More literature K2G General-Purpose (GP) EVM Quick Start Guide (Rev. A) 2017年 7月 27日
White paper Voice as the user interface – a new era in speech processing white Paper 2017年 5月 9日
Application note Processor SDK RTOS Audio Benchmark Starter Kit 2017年 4月 12日
User guide K2G Industrial Communications Engine (K2G ICE) 2017年 2月 28日
More literature K2G Industrial Communications Engine (ICE) Quick Start Guide 2017年 2月 2日
User guide TPS659118 User’s Guide for 66AK2G02 Processor 2016年 5月 2日
Application note SERDES Link Commissioning on KeyStone I and II Devices 2016年 4月 13日
More literature K2G Audio Daughter Card Quick Start Guide 2016年 3月 14日
White paper Multicore SoCs stay a step ahead of SoC FPGAs 2016年 2月 23日
Application note TI DSP Benchmarking 2016年 1月 13日
Application note Keystone II DDR3 Debug Guide 2015年 10月 16日
Application note Keystone II DDR3 Initialization 2015年 1月 26日
Application note Hardware Design Guide for KeyStone II Devices 2014年 3月 24日
User guide C66x CorePac User's Guide (Rev. C) 2013年 6月 28日
Application note Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011年 5月 19日
User guide C66x CPU and Instruction Set Reference Guide 2010年 11月 9日
User guide C66x DSP Cache User's Guide 2010年 11月 9日

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子卡

AUDK2G — 66AK2Gx (K2G) 音訊子卡

The K2G audio daughter card is designed to work in conjunction with the K2G general-purpose EVM (EVMK2G) or EVMK2GX and the EVMK2G or EVMK2GX is required for audio daughter card operation.  The daughter card allows users to develop multichannel audio applications such as A/V receivers, (...)

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EVMK2GX — 66AK2Gx 1GHz 評估模組

The EVMK2GX (also known as "K2G") 1GHz evaluation module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)

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EVMK2GXS — 66AK2Gx (K2G) 1 GHz 高安全性評估模組

The K2G 1GHz High Secure Evaluation Module (EVM) enables developers to start  evaluating and testing the programming of the  high secure developmental version of the  66AK2Gx processor, and to accelerate the next stage of secure boot product development of audio and industrial real (...)

使用指南: PDF
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-K2G — Linux Processor SDK for K2Gx

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and (...)

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PROCESSOR-SDK-LINUX-RT-K2G — Linux-RT Processor SDK for K2G

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and (...)

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PROCESSOR-SDK-RTOS-K2G — TI-RTOS Processor SDK for K2Gx (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and (...)

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AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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Arm 式處理器
66AK2G12 — 高效能多核心 DSP+Arm - 1x Arm A15 核心、1x C66x DSP 核心
數位訊號處理器 (DSP)
DM505 — 適用視覺分析 15mm 封裝的 SoC SM320C6201-EP — 增強型產品 C6201 定點 DSP SM320C6415-EP — 強化型產品 C6415 定點 DSP SM320C6424-EP — 強化型產品 C6424 定點 DSP SM320C6455-EP — 強化型產品 C6455 定點 DSP SM320C6472-HIREL — 高可靠性產品 6 核心 C6472 定點 DSP SM320C6678-HIREL — 高可靠性產品高效能 8 核心 C6678 定點和浮點 DSP SM320C6701 — 軍用應用的單核 C67x 浮點 DSP - 高達 167MHz SM320C6701-EP — 增強型產品 C6701 浮點 DSP SM320C6711D-EP — 增強型產品 C6711D 浮點 DSP SM320C6712D-EP — 增強型產品 C6712D DSP SM320C6713B-EP — 強化型產品 C6713 浮點 DSP SM320C6727B — 軍用級 C6727B 浮點 DSP SM320C6727B-EP — 強化型產品 C6727 浮點 DSP SMJ320C6201B — 軍用定點數位訊號處理器 SMJ320C6203 — 軍用級 C62x 定點 DSP - 陶瓷封裝 SMJ320C6701 — 軍用級 C67x 浮點 DSP - 陶瓷封裝 SMJ320C6701-SP — 航太級 C6701 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 SMV320C6727B-SP — 航太級 C6727B 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 TMS320C5517 — 低功耗 C55x 定點 DSP - 高達 200MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C5532 — 低功耗 C55x 定點 DSP - 高達 100MHz TMS320C5533 — 低功耗 C55x 定點 DSP - 高達 100MHz、USB TMS320C5534 — 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面 TMS320C5535 — 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C6202B — C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B — C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 — 定點數位訊號處理器 TMS320C6205 — 定點數位訊號處理器 TMS320C6211B — C62x 定點 DSP - 高達 167MHz TMS320C6414 — C64x 定點 DSP - 高達 720MHz、McBSP TMS320C6415 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI TMS320C6416 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q — C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424Q — C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6454 — C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6457 — 通訊基礎設施數位訊號處理器 TMS320C6701 — C67x 浮點 DSP - 高達 167MHz、McBSP TMS320C6711D — C67x 浮點 DSP - 高達 250MHz、McBSP、32 位元 EMIFA TMS320C6712D — C67x 浮點 DSP - 高達 150MHz、McBSP、16 位元 EMIFA TMS320C6720 — C67x 浮點 DSP - 200MHz、McASP、16 位元 EMIFA TMS320C6722B — C67x 浮點 DSP - 高達 250MHz、McASP、16 位元 EMIFA TMS320C6726B — C67x 浮點 DSP - 高達 266MHz、McASP、16 位元 EMIFA TMS320C6727 — C67x 浮點 DSP - 高達 250MHz、McASP、32 位元 EMIFA TMS320C6727B — C67x 浮點 DSP - 高達 350MHz、McASP、32 位元 EMIFA TMS320C6743 — 低功耗 C674x 浮點 DSP- 375MHz TMS320C6745 — 低功耗 C674x 浮點 DSP- 456MHz，QFP TMS320C6747 — 低功耗 C674x 浮點 DSP- 456MHz，PBGA TMS320DM642Q — 視訊/成像定點數位訊號處理器 TMS320DM6431Q — 數位媒體處理器，高達 2400 MIPS、300 MHz 時脈速率 TMS320DM6435Q — 數位媒體處理器，最高達 4800 MIPS、600 MHz 時脈速率、1 McASP、1 McBSP TMS320DM6437Q — 數位媒體處理器，最高達 4800 MIPS、600 MHz 時脈速率、1 個 McASP、2 個 McBSP TMS320DM6441 — DaVinci 數位媒體晶片系統 TMS320DM6467T — 數位媒體晶片系統 TMS320DM647 — 數位媒體處理器
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驅動程式或資料庫

FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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支援產品和硬體

產品
Arm 式處理器
66AK2G12 — 高效能多核心 DSP+Arm - 1x Arm A15 核心、1x C66x DSP 核心
數位訊號處理器 (DSP)
DM505 — 適用視覺分析 15mm 封裝的 SoC SM320C6201-EP — 增強型產品 C6201 定點 DSP SM320C6415-EP — 強化型產品 C6415 定點 DSP SM320C6424-EP — 強化型產品 C6424 定點 DSP SM320C6455-EP — 強化型產品 C6455 定點 DSP SM320C6472-HIREL — 高可靠性產品 6 核心 C6472 定點 DSP SM320C6678-HIREL — 高可靠性產品高效能 8 核心 C6678 定點和浮點 DSP SM320C6701 — 軍用應用的單核 C67x 浮點 DSP - 高達 167MHz SM320C6701-EP — 增強型產品 C6701 浮點 DSP SM320C6711D-EP — 增強型產品 C6711D 浮點 DSP SM320C6712D-EP — 增強型產品 C6712D DSP SM320C6713B-EP — 強化型產品 C6713 浮點 DSP SM320C6727B — 軍用級 C6727B 浮點 DSP SM320C6727B-EP — 強化型產品 C6727 浮點 DSP SMJ320C6201B — 軍用定點數位訊號處理器 SMJ320C6203 — 軍用級 C62x 定點 DSP - 陶瓷封裝 SMJ320C6701 — 軍用級 C67x 浮點 DSP - 陶瓷封裝 SMJ320C6701-SP — 航太級 C6701 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 SMV320C6727B-SP — 航太級 C6727B 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 TMS320C5517 — 低功耗 C55x 定點 DSP - 高達 200MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C5532 — 低功耗 C55x 定點 DSP - 高達 100MHz TMS320C5533 — 低功耗 C55x 定點 DSP - 高達 100MHz、USB TMS320C5534 — 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面 TMS320C5535 — 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C6202B — C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B — C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 — 定點數位訊號處理器 TMS320C6205 — 定點數位訊號處理器 TMS320C6211B — C62x 定點 DSP - 高達 167MHz TMS320C6414 — C64x 定點 DSP - 高達 720MHz、McBSP TMS320C6415 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI TMS320C6416 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q — C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424Q — C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6454 — C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6457 — 通訊基礎設施數位訊號處理器 TMS320C6701 — C67x 浮點 DSP - 高達 167MHz、McBSP TMS320C6711D — C67x 浮點 DSP - 高達 250MHz、McBSP、32 位元 EMIFA TMS320C6712D — C67x 浮點 DSP - 高達 150MHz、McBSP、16 位元 EMIFA TMS320C6720 — C67x 浮點 DSP - 200MHz、McASP、16 位元 EMIFA TMS320C6722B — C67x 浮點 DSP - 高達 250MHz、McASP、16 位元 EMIFA TMS320C6726B — C67x 浮點 DSP - 高達 266MHz、McASP、16 位元 EMIFA TMS320C6727 — C67x 浮點 DSP - 高達 250MHz、McASP、32 位元 EMIFA TMS320C6727B — C67x 浮點 DSP - 高達 350MHz、McASP、32 位元 EMIFA TMS320C6743 — 低功耗 C674x 浮點 DSP- 375MHz TMS320C6745 — 低功耗 C674x 浮點 DSP- 456MHz，QFP TMS320C6747 — 低功耗 C674x 浮點 DSP- 456MHz，PBGA TMS320DM642Q — 視訊/成像定點數位訊號處理器 TMS320DM6431Q — 數位媒體處理器，高達 2400 MIPS、300 MHz 時脈速率 TMS320DM6435Q — 數位媒體處理器，最高達 4800 MIPS、600 MHz 時脈速率、1 McASP、1 McBSP TMS320DM6437Q — 數位媒體處理器，最高達 4800 MIPS、600 MHz 時脈速率、1 個 McASP、2 個 McBSP TMS320DM6441 — DaVinci 數位媒體晶片系統 TMS320DM6467T — 數位媒體晶片系統 TMS320DM647 — 數位媒體處理器
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PRU-ICSS-INDUSTRIAL-SW — 適用於 Sitara™ 處理器的 PRU-ICSS 工業軟體

PRU-ICSS 通訊協定啟用 TI Sitara 處理器的即時工業通訊功能。PRU-ICSS 通訊協定可在 Processor-SDK-RTOS、TI 的統合軟體開發平台上使用，並且包含最佳化 PRU-ICSS 韌體，這是適用於 ARM 處理器及範例應用的對應 PRU-ICSS 驅動程式。PRU-ICSS 韌體可在 PRU 核心上執行，從主 ARM 處理器卸載時間關鍵連結層處理，執行 TI-RTOS。PRU-ICSS 驅動程式提供簡單的 PRU-ICSS 資源存取，並可輕鬆與在 ARM 核心上執行的通訊協定堆疊和應用軟體整合。這些範例會進一步說明如何將低階韌體與通訊協定堆疊和應用軟體整合。

(...)

使用指南: PDF
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驅動程式或資料庫

VOLIB — Voice library (VoLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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產品
Arm 式處理器
66AK2G12 — 高效能多核心 DSP+Arm - 1x Arm A15 核心、1x C66x DSP 核心
數位訊號處理器 (DSP)
DM505 — 適用視覺分析 15mm 封裝的 SoC SM320C6201-EP — 增強型產品 C6201 定點 DSP SM320C6415-EP — 強化型產品 C6415 定點 DSP SM320C6424-EP — 強化型產品 C6424 定點 DSP SM320C6455-EP — 強化型產品 C6455 定點 DSP SM320C6472-HIREL — 高可靠性產品 6 核心 C6472 定點 DSP SM320C6678-HIREL — 高可靠性產品高效能 8 核心 C6678 定點和浮點 DSP SM320C6701 — 軍用應用的單核 C67x 浮點 DSP - 高達 167MHz SM320C6701-EP — 增強型產品 C6701 浮點 DSP SM320C6711D-EP — 增強型產品 C6711D 浮點 DSP SM320C6712D-EP — 增強型產品 C6712D DSP SM320C6713B-EP — 強化型產品 C6713 浮點 DSP SM320C6727B — 軍用級 C6727B 浮點 DSP SM320C6727B-EP — 強化型產品 C6727 浮點 DSP SMJ320C6201B — 軍用定點數位訊號處理器 SMJ320C6203 — 軍用級 C62x 定點 DSP - 陶瓷封裝 SMJ320C6701 — 軍用級 C67x 浮點 DSP - 陶瓷封裝 SMJ320C6701-SP — 航太級 C6701 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 SMV320C6727B-SP — 航太級 C6727B 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 TMS320C5517 — 低功耗 C55x 定點 DSP - 高達 200MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C5532 — 低功耗 C55x 定點 DSP - 高達 100MHz TMS320C5533 — 低功耗 C55x 定點 DSP - 高達 100MHz、USB TMS320C5534 — 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面 TMS320C5535 — 低功耗 C55x 定點 DSP - 高達 100MHz、USB、LCD 介面、FFT HWA、SAR ADC TMS320C6202B — C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B — C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 — 定點數位訊號處理器 TMS320C6205 — 定點數位訊號處理器 TMS320C6211B — C62x 定點 DSP - 高達 167MHz TMS320C6414 — C64x 定點 DSP - 高達 720MHz、McBSP TMS320C6415 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI TMS320C6416 — C64x 定點 DSP - 高達 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q — C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424Q — C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6454 — C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6457 — 通訊基礎設施數位訊號處理器 TMS320C6701 — C67x 浮點 DSP - 高達 167MHz、McBSP TMS320C6711D — C67x 浮點 DSP - 高達 250MHz、McBSP、32 位元 EMIFA TMS320C6712D — C67x 浮點 DSP - 高達 150MHz、McBSP、16 位元 EMIFA TMS320C6720 — C67x 浮點 DSP - 200MHz、McASP、16 位元 EMIFA TMS320C6722B — C67x 浮點 DSP - 高達 250MHz、McASP、16 位元 EMIFA TMS320C6726B — C67x 浮點 DSP - 高達 266MHz、McASP、16 位元 EMIFA TMS320C6727 — C67x 浮點 DSP - 高達 250MHz、McASP、32 位元 EMIFA TMS320C6727B — C67x 浮點 DSP - 高達 350MHz、McASP、32 位元 EMIFA TMS320C6743 — 低功耗 C674x 浮點 DSP- 375MHz TMS320C6745 — 低功耗 C674x 浮點 DSP- 456MHz，QFP TMS320C6747 — 低功耗 C674x 浮點 DSP- 456MHz，PBGA TMS320DM642Q — 視訊/成像定點數位訊號處理器 TMS320DM6431Q — 數位媒體處理器，高達 2400 MIPS、300 MHz 時脈速率 TMS320DM6435Q — 數位媒體處理器，最高達 4800 MIPS、600 MHz 時脈速率、1 McASP、1 McBSP TMS320DM6437Q — 數位媒體處理器，最高達 4800 MIPS、600 MHz 時脈速率、1 個 McASP、2 個 McBSP TMS320DM6441 — DaVinci 數位媒體晶片系統 TMS320DM6467T — 數位媒體晶片系統 TMS320DM647 — 數位媒體處理器
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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軟體轉碼器

AURO-3P-3DENGINE — Auro Technologies Auro 轉碼器和 Auro-Matic 軟體

Auro Technologies’ Auro-Engine includes their Auro-Codec and Auro-Matic elements for real time audio stream encoding and up mixing affording 3D audio user experiences. The Auro-Codec and Auro-Matic algorithms have been ported to select TI C6x DSPs.
從：Auro Technologies N.V.
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模擬型號

66AK2G12 BSDL Model

SPRM715.ZIP (24 KB) - BSDL Model
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模擬型號

66AK2G12 IBIS Model

SPRM705.ZIP (1918 KB) - IBIS Model
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模擬型號

66AK2G12 Thermal Model

SPRM716.ZIP (3 KB) - Thermal Model
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模擬型號

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
lock = 需要匯出核准 (1 分鐘)
lock 下載
計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
使用指南: PDF
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參考設計

TIDEP-0088 — 適用於基於語音的應用的音訊預處理系統參考設計

This reference design uses multiple microphones, a beamforming algorithm, and other processes to extract clear speech and audio amidst noise and other clutter.  The rapid increase in applications that are used in noise-prone environments for voice activated digital assitants creates demand (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0069 — 66AK2Gx DSP + ARM 處理器音訊處理參考設計

This reference design is a reference platform based on the 66AK2Gx DSP + ARM processor  System-On-Chip (SoC) and companion AIC3106 Audio codec and enables a quick path to audio processing algorithm design and demonstration. This audio solution design includes real time application software (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0067 — 66AK2Gx DSP + ARM 處理器電源解決方案參考設計

This reference design is  based on the 66AK2Gx multicore System-on-Chip (SoC) processor and companion TPS65911 power management integrated circuit (PMIC) which includes power supplies and power sequencing for the 66AK2Gx processor in a single device. This power solution design also includes (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0068 — 適用於 K2G 通用 EVM (GP EVM) 的 PCI-Express PCB 設計注意事項參考設計

PCI-Express provides for low pin-count, high reliability, and high-speed with data transfer at rates of up to 5.0 Gbps per lane, per direction, and an PCIe module is included on the TI 66AK2Gx DSP + ARM Processor system on chip (SoC).  This PCIe PCB design considerations reference design  (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0070 — 用於在 66AK2Gx 系統中提高記憶體可靠性的 DDR ECC 參考設計

This reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2Gx Multicore DSP + ARM processor System-on-Chip (SoC).  It enables developers to implement a high (...)
Design guide: PDF
電路圖: PDF
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  • 認證摘要
  • 進行中持續性的可靠性監測
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