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線性與低壓差 (LDO) 穩壓器

TPS74201

現行

1.5-A、低 VIN (0.8-V)、低雜訊、高 PSRR、可調式超低壓降電壓穩壓器

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產品規格表

TPS74201

現行
產品規格表 立即訂購

產品詳細資料

Output options Adjustable Output Iout (max) (A) 1.5 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.5 Vout (min) (V) 0.8 Rating Catalog Noise (µVrms) 13 PSRR at 100 KHz (dB) 52 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 27 Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 1 Dropout voltage (Vdo) (typ) (mV) 55 Operating temperature range (°C) -40 to 125
Output options Adjustable Output Iout (max) (A) 1.5 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.5 Vout (min) (V) 0.8 Rating Catalog Noise (µVrms) 13 PSRR at 100 KHz (dB) 52 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 27 Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 1 Dropout voltage (Vdo) (typ) (mV) 55 Operating temperature range (°C) -40 to 125
TO-263 (KTW) 7 153.924 mm² 10.1 x 15.24 VQFN (RGR) 20 12.25 mm² 3.5 x 3.5 VQFN (RGW) 20 25 mm² 5 x 5
  • Input voltage range: 0.8V to 5.5V
  • Soft-Start (SS) pin provides a linear start-up with ramp time set by external capacitor
  • 1% accuracy over line, load, and temperature
  • Supports input voltages as low as 0.8V with external bias supply
  • Adjustable output (0.8V to 3.6V)
  • Ultra-Low Dropout:
    • 60mV (legacy chip) at 1.5A (typical)
    • 55mV (new chip) at 1.5A (typical)
  • Stable with any output capacitor ≥ 2.2µF (new chip)
  • Stable with any or no output capacitor (legacy chip)
  • Excellent transient response
  • Open-Drain Power-Good
  • Active high enable
  • Input voltage range: 0.8V to 5.5V
  • Soft-Start (SS) pin provides a linear start-up with ramp time set by external capacitor
  • 1% accuracy over line, load, and temperature
  • Supports input voltages as low as 0.8V with external bias supply
  • Adjustable output (0.8V to 3.6V)
  • Ultra-Low Dropout:
    • 60mV (legacy chip) at 1.5A (typical)
    • 55mV (new chip) at 1.5A (typical)
  • Stable with any output capacitor ≥ 2.2µF (new chip)
  • Stable with any or no output capacitor (legacy chip)
  • Excellent transient response
  • Open-Drain Power-Good
  • Active high enable

The TPS742 series of low-dropout (LDO) linear regulators provide an easy-to-use, robust power-management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. The device is is stable with any type of capacitor greater than or equal to 2.2µF (new chip only), and is fully specified from –40°C to 125°C.

The TPS742 series of low-dropout (LDO) linear regulators provide an easy-to-use, robust power-management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. The device is is stable with any type of capacitor greater than or equal to 2.2µF (new chip only), and is fully specified from –40°C to 125°C.
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類型 標題 日期
* Data sheet TPS742 1.5A Ultra-LDO With Programmable Soft-Start datasheet (Rev. O) PDF | HTML 2024年 10月 18日
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020年 8月 18日
Application note Using Thermal Calculation Tools for Analog Components (Rev. A) 2019年 8月 30日
Application note A Topical Index of TI LDO Application Notes (Rev. F) 2019年 6月 27日
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
Application note LDO Performance Near Dropout 2010年 10月 8日
Application note Using New Thermal Metrics 2009年 12月 15日
Analog Design Journal Q3 2007 Issue Analog Applications Journal 2007年 8月 10日
Analog Design Journal Simultaneous power-down sequencing with the TPS74x01 family of linear regulators 2007年 8月 10日
Analog Design Journal A 3-A, 1.2-Vout linear regulator with 80% efficiency and Plost < 1W 2006年 10月 10日
EVM User's guide TPS74x01EVM-118 User's Guide 2006年 6月 20日

設計與開發

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ADC 各通道的輸入預設連接至變壓器輸入電路，其可連接至 50-Ω 單端訊號來源。時鐘參考輸入可透過變壓器輸入提供，並可連接至 50-Ω 單端時鐘來源。板載 LMK04828 可用於產生必要的 JESD204B 時鐘。透過板載 USB 連線和 Windows® 版 GUI (...)

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模擬型號

TPS74201 PSpice Transient Model (Rev. B)

SLIM016B.ZIP (61 KB) - PSpice Model
下載
模擬型號

TPS74201 TINA-TI Transient Reference Design

SLIM289.TSC (106 KB) - TINA-TI Reference Design
下載
模擬型號

TPS74201 TINA-TI Transient Spice Model

SLIM288.ZIP (36 KB) - TINA-TI Spice Model
下載
模擬型號

TPS74201 Unencrypted PSpice Transient Model

SBVM620.ZIP (3 KB) - PSpice Model
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參考設計

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Design guide: PDF
電路圖: PDF
參考設計

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電路圖: PDF
參考設計

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In TIDA-00684 reference design a quad-channel TSW3080 evaluation module (EVM) is developed to shows how to use an active amplifier interface with the DAC38J84 to demonstrate an arbitrary-waveform-generator frontend. The DAC38J84 provides four DAC channels with 16 bits of resolution with a maximum (...)
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電路圖: PDF
參考設計

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電路圖: PDF
參考設計

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電路圖: PDF
參考設計

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使用指南: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TO-263 (KTW) 7 Ultra Librarian
VQFN (RGR) 20 Ultra Librarian
VQFN (RGW) 20 Ultra Librarian
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