TMS570LS0714-S

ACTIVE

High Performance 32-bit ARM Cortex-R5 based Microcontroller

TMS570LS0714-S

ACTIVE

Product details

Frequency (MHz) 160 Flash memory (kByte) 786 RAM (kByte) 128 ADC type 2 x 12-bit (24ch) Number of GPIOs 64 UART 2 Features Hercules high-performance microcontroller TI functional safety category Functional Safety-Compliant Operating temperature range (°C) -40 to 125 Ethernet No PWM (Ch) 54 SPI 1 CAN (#) 3 Power supply solution TPS65381A-Q1 Communication interface CAN, SPI, UART
Frequency (MHz) 160 Flash memory (kByte) 786 RAM (kByte) 128 ADC type 2 x 12-bit (24ch) Number of GPIOs 64 UART 2 Features Hercules high-performance microcontroller TI functional safety category Functional Safety-Compliant Operating temperature range (°C) -40 to 125 Ethernet No PWM (Ch) 54 SPI 1 CAN (#) 3 Power supply solution TPS65381A-Q1 Communication interface CAN, SPI, UART
LQFP (PGE) 144 484 mm² 22 x 22
  • High-Performance Automotive-Grade Microcontroller (MCU) for Safety-Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU and On-chip RAMs
    • Error Signaling Module With Error Pin
    • Voltage and Clock Monitoring
  • ARM Cortex-R4F 32-Bit RISC CPU
    • 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single and Double Precision
    • 12-Region Memory Protection Unit (MPU)
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • Up to 160-MHz System Clock
    • Core Supply Voltage (VCC): 1.14 to 1.32 V
    • I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
  • Integrated Memory
    • 768KB of Flash With ECC
    • 128KB of RAM With ECC
    • 64KB of Flash for Emulated EEPROM With ECC
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt Timer (RTI) OS Timer
    • 128-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Peripheral Requests
    • Parity for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
  • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
  • Advanced JTAG Security Module (AJSM)
  • Up to 64 General-Purpose I/O (GIO) Pins
    • Up to 16 GIO Pins With Interrupt Generation Capability
  • Enhanced Timing Peripherals
    • 7 Enhanced Pulse Width Modulator (ePWM) Modules
    • 6 Enhanced Capture (eCAP) Modules
    • 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Two Next Generation High-End Timer (N2HET) Modules
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM With Parity Protection Each
    • Each N2HET Includes Hardware Angle Generator
    • Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET
  • Two 12-Bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels
    • 16 Shared Channels
    • 64 Result Buffers With Parity Protection Each
  • Multiple Communication Interfaces
    • Up to Three CAN Controllers (DCANs)
      • 64 Mailboxes With Parity Protection Each
      • Compliant to CAN Protocol Version 2.0A and 2.0B
    • Inter-Integrated Circuit (I2C)
    • 3 Multibuffered Serial Peripheral Interfaces (MibSPIs)
      • 128 Words With Parity Protection Each
      • 8 Transfer Groups
    • One Standard Serial Peripheral Interface (SPI) Module
    • Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN 2.1) Interface Support
  • Packages
    • 144-Pin Quad Flatpack (PGE) [Green]
    • 100-Pin Quad Flatpack (PZ) [Green]

All trademarks are the property of their respective owners.

  • High-Performance Automotive-Grade Microcontroller (MCU) for Safety-Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU and On-chip RAMs
    • Error Signaling Module With Error Pin
    • Voltage and Clock Monitoring
  • ARM Cortex-R4F 32-Bit RISC CPU
    • 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single and Double Precision
    • 12-Region Memory Protection Unit (MPU)
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • Up to 160-MHz System Clock
    • Core Supply Voltage (VCC): 1.14 to 1.32 V
    • I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
  • Integrated Memory
    • 768KB of Flash With ECC
    • 128KB of RAM With ECC
    • 64KB of Flash for Emulated EEPROM With ECC
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt Timer (RTI) OS Timer
    • 128-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Peripheral Requests
    • Parity for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
  • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
  • Advanced JTAG Security Module (AJSM)
  • Up to 64 General-Purpose I/O (GIO) Pins
    • Up to 16 GIO Pins With Interrupt Generation Capability
  • Enhanced Timing Peripherals
    • 7 Enhanced Pulse Width Modulator (ePWM) Modules
    • 6 Enhanced Capture (eCAP) Modules
    • 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Two Next Generation High-End Timer (N2HET) Modules
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM With Parity Protection Each
    • Each N2HET Includes Hardware Angle Generator
    • Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET
  • Two 12-Bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels
    • 16 Shared Channels
    • 64 Result Buffers With Parity Protection Each
  • Multiple Communication Interfaces
    • Up to Three CAN Controllers (DCANs)
      • 64 Mailboxes With Parity Protection Each
      • Compliant to CAN Protocol Version 2.0A and 2.0B
    • Inter-Integrated Circuit (I2C)
    • 3 Multibuffered Serial Peripheral Interfaces (MibSPIs)
      • 128 Words With Parity Protection Each
      • 8 Transfer Groups
    • One Standard Serial Peripheral Interface (SPI) Module
    • Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN 2.1) Interface Support
  • Packages
    • 144-Pin Quad Flatpack (PGE) [Green]
    • 100-Pin Quad Flatpack (PZ) [Green]

All trademarks are the property of their respective owners.

The TMS570LS0714 device is part of the Hercules TMS570 series of high-performance automotive-grade ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the development of ISO 26262 and IEC 61508 functional safety applications. Start evaluating today with the Hercules Hercules TMS570 LaunchPad Development Kit. The TMS570LS0714 device has on-chip diagnostic features including: dual CPUs in lockstep; CPU and memory Built-In Self-Test (BIST) logic; ECC on both the flash and the SRAM; parity on peripheral memories; and loopback capability on most peripheral I/Os.

The TMS570LS0714 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 160 MHz providing up to 265 DMIPS. The TMS570 device supports the word invariant big-endian [BE32] format.

The TMS570LS0714 device has 768KB of integrated flash and 128KB of RAM configurations with single-bit error correction and double-bit error detection. The flash memory on this device is nonvolatile, electrically erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as the I/O supply) for all read, program, and erase operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and doubleword modes throughout the supported frequency range.

The TMS570LS0714 device features peripherals for real-time control-based applications, including two Next-Generation High-End Timer (N2HET) timing coprocessors with up to 44 total I/O terminals, seven Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or intervention. The ePWM is easy to use and supports complementary PWMs and deadband generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM is ideal for digital motor control applications.

The eCAP module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or to generate simple PWM when not needed for capture applications.

The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems.

The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. There are three separate groups. Each group can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs; two SPIs; two SCIs, one of which can be used as LIN; up to three DCANs; and one I2C module. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C module supports speeds of 100 and 400 kbps.

A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides one of the six possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) circuit that when enabled, outputs a continuous external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors device errors and determines whether an interrupt or external error signal (nERROR) is asserted when a fault is detected. The nERROR terminal can be monitored externally as an indicator of a fault condition in the microcontroller.

With integrated functional safety features and a wide choice of communication and control peripherals, the TMS570LS0714 device is an ideal solution for high-performance, real-time control applications with safety-critical

The TMS570LS0714 device is part of the Hercules TMS570 series of high-performance automotive-grade ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the development of ISO 26262 and IEC 61508 functional safety applications. Start evaluating today with the Hercules Hercules TMS570 LaunchPad Development Kit. The TMS570LS0714 device has on-chip diagnostic features including: dual CPUs in lockstep; CPU and memory Built-In Self-Test (BIST) logic; ECC on both the flash and the SRAM; parity on peripheral memories; and loopback capability on most peripheral I/Os.

The TMS570LS0714 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 160 MHz providing up to 265 DMIPS. The TMS570 device supports the word invariant big-endian [BE32] format.

The TMS570LS0714 device has 768KB of integrated flash and 128KB of RAM configurations with single-bit error correction and double-bit error detection. The flash memory on this device is nonvolatile, electrically erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as the I/O supply) for all read, program, and erase operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and doubleword modes throughout the supported frequency range.

The TMS570LS0714 device features peripherals for real-time control-based applications, including two Next-Generation High-End Timer (N2HET) timing coprocessors with up to 44 total I/O terminals, seven Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or intervention. The ePWM is easy to use and supports complementary PWMs and deadband generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM is ideal for digital motor control applications.

The eCAP module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or to generate simple PWM when not needed for capture applications.

The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems.

The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. There are three separate groups. Each group can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs; two SPIs; two SCIs, one of which can be used as LIN; up to three DCANs; and one I2C module. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C module supports speeds of 100 and 400 kbps.

A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides one of the six possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) circuit that when enabled, outputs a continuous external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors device errors and determines whether an interrupt or external error signal (nERROR) is asserted when a fault is detected. The nERROR terminal can be monitored externally as an indicator of a fault condition in the microcontroller.

With integrated functional safety features and a wide choice of communication and control peripherals, the TMS570LS0714 device is an ideal solution for high-performance, real-time control applications with safety-critical

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Technical documentation

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Type Title Date
* Data sheet TMS570LS0714 16- and 32-Bit RISC Flash Microcontroller datasheet (Rev. E) PDF | HTML 10 Nov 2016
* Errata TMS570LS09/07xx Microcontroller Silicon Errata (Silicon Rev 0) (Rev. D) 31 May 2016
* Errata TMS570LS09/07xx Microcontroller Silicon Errata (Silicon Rev A) (Rev. B) 31 May 2016
* User guide TMS570LS09x/07x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (Rev. A) 01 Mar 2018
Functional safety information Certification for Functional Safety Hardware Process (Rev. B) 09 Jun 2022
More literature Hercules™ Diagnostic Library Test Automation Unit User Guide (Rev. B) PDF | HTML 09 Jan 2020
More literature HALCoGen-CSP 04.07.01 (Rev. C) PDF | HTML 08 Jan 2020
Functional safety information HALCoGen-CSP Installation Guide (Rev. B) PDF | HTML 08 Jan 2020
Functional safety information HALCoGen-CSP User's Guide (Rev. C) PDF | HTML 08 Jan 2020
Functional safety information Hercules Diagnostic Library -TAU Installation Guide (Rev. B) PDF | HTML 08 Jan 2020
User guide Hercules Diagnostic Library CSP Without LDRA 29 Oct 2019
More literature Diagnostic Library CSP Release Notes 17 Oct 2019
Functional safety information SafeTI™ Hercules™ Diagnostic Library Release Notes (Rev. A) 24 Sep 2019
Application note Hercules PLL Advisory SSWF021#45 Workaround (Rev. B) PDF | HTML 09 Sep 2019
Application note CAN Bus Bootloader for Hercules Microcontrollers PDF | HTML 21 Aug 2019
Application note HALCoGen CSP Without LDRA Release_Notes 19 Aug 2019
User guide HALCoGen-CSP Without LDRA Installation Guide PDF | HTML 19 Aug 2019
User guide HALCoGen-CSP Without LDRA User's Guide PDF | HTML 19 Aug 2019
User guide Hercules Diagnostic Library - Without LDRA Installation Guide PDF | HTML 19 Aug 2019
User guide Hercules™ Diag Lib Test Automation Unit Without LDRA User's Guide PDF | HTML 19 Aug 2019
Functional safety information Certification for SafeTI Functional Safety Hardware Process (Rev. A) 07 Jun 2019
Application note Interfacing the Embedded 12-Bit ADC in a TMS570LS31x/21x and RM4x Series MCUs (Rev. A) 20 Apr 2018
Application note FreeRTOS on Hercules Devices_new 19 Apr 2018
Application note Sharing FEE Blocks Between the Bootloader and the Application 07 Nov 2017
User guide Hercules™ TMS570LS12x/RM46 LaunchPad User's Guide 31 May 2017
Certificate TUEV SUED Certificate for TMS570LS09X/07x (Rev. A) 28 Mar 2017
Application note Sharing Exception Vectors on Hercules™ Based Microcontrollers 27 Mar 2017
Functional safety information Safety Manual for TMS570LS07x/09x Hercules ARM Safety Critical MCUs (Rev. A) 12 Dec 2016
Application note Hercules AJSM Unlock (Rev. A) PDF | HTML 19 Oct 2016
Application note How to Create a HALCoGen Based Project For CCS (Rev. B) 09 Aug 2016
Application note Using the CRC Module on Hercules™-Based Microcontrollers 04 Aug 2016
Application note Migrating from TMS570LS12x/11x to TMS570LS09x/07x MCUs (Rev. A) 15 Jun 2016
Functional safety information Functional Safety Audit: SafeTI Functional Safety Hardware Development (Rev. A) 25 Apr 2016
Application note High Speed Serial Bus Using the MibSPIP Module on Hercules-Based MCUs 22 Apr 2016
Functional safety information Enabling Functional Safety Using SafeTI Diagnostic Library 18 Dec 2015
Functional safety information Safety Manual for TMS570LS12x/11x Hercules ARM Safety Critical MCUs (Rev. B) 11 Dec 2015
White paper Hercules™ MCU: Features Applicable to Use in High-Speed Rail 02 Nov 2015
Application note Triggering ADC Using Internal Timer Events on Hercules MCUs 19 Oct 2015
White paper Extending TI’s Hercules MCUs with the integrated flexible HET 29 Sep 2015
Application note Continuous Monitor of the PLL Frequency With the DCC 24 Jul 2015
Application note PWM Generation and Input Capture Using HALCoGen N2HET Module 30 Jun 2015
Functional safety information Foundational Software for Functional Safety 12 May 2015
Application note Sine Wave Generation Using PWM With Hercules N2HET and HTU 12 May 2015
Application note Triangle/Trapezoid Wave Generation Using PWM With Hercules N2HET 01 May 2015
Application note Nested Interrupts on Hercules ARM Cortex-R4/5-Based Microncontrollers 23 Apr 2015
White paper Latch-Up White Paper PDF | HTML 22 Apr 2015
Application note Interrupt and Exception Handling on Hercules ARM Cortex-R4/5-Based MCUs 20 Apr 2015
Application note Monitoring PWM Using N2HET 02 Apr 2015
Application note Hercules SCI With DMA 22 Mar 2015
Certificate TÜV NORD Certificate for Functional Safety Software Development Process 03 Feb 2015
Functional safety information Calculating Equivalent Power-on-Hours for Hercules Safety MCUs 26 Jan 2015
Application note Limiting Clamp Currents on TMS470/TMS570 Digital and Analog Inputs (Rev. A) 08 Dec 2014
Functional safety information TUV SUD ISO-13849 Safety Architecture Concept Study 02 Jul 2014
More literature HaLCoGen Release Notes 25 Jun 2014
Application note Interfacing TPS65381 With Hercules Microcontrollers (Rev. A) 14 Feb 2014
User guide TMS570LS12x Hercules Development Kit (HDK) User's Guide (Rev. A) 10 Oct 2013
Functional safety information IEC 60730 and UL 1998 Safety Standard Compliance Made Easier with TI Hercules 03 Oct 2013
Application note CAN Bus Bootloader for TMS570LS12X MCU 16 Sep 2013
Application note SPI Bootloader for Hercules TMS570LS12X MCU 16 Sep 2013
Application note UART Bootloader for Hercules TMS570LS12X MCU 16 Sep 2013
White paper Model-Based Tool Qualification of the TI C/C++ ARM® Compiler 06 Jun 2013
Application note Initialization of Hercules ARM Cortex-R4F Microcontrollers (Rev. D) 29 May 2013
Functional safety information Accelerating safety-certified motor control designs (Rev. A) 04 Oct 2012
Application note Hercules Family Frequency Slewing to Reduce Voltage and Current Transients 05 Jul 2012
Application note Basic PBIST Configuration and Influence on Current Consumption (Rev. C) 12 Apr 2012
Application note Verification of Data Integrity Using CRC 17 Feb 2012
User guide HET Integrated Development Environment User's Guide (Rev. A) 17 Nov 2011
Functional safety information Important ARM Ltd Application Notes for TI Hercules ARM Safety MCUs 17 Nov 2011
Functional safety information Execution Time Measurement for Hercules ARM Safety MCUs (Rev. A) 04 Nov 2011
Application note Use of All 1'’s and All 0's Valid in Flash EEPROM Emulation 27 Sep 2011
Application note 3.3 V I/O Considerations for Hercules Safety MCUs (Rev. A) 06 Sep 2011
Functional safety information ADC Source Impedance for Hercules ARM Safety MCUs (Rev. B) 06 Sep 2011
Functional safety information Configuring a CAN Node on Hercules ARM Safety MCUs 06 Sep 2011
Functional safety information Configuring the Hercules ARM Safety MCU SCI/LIN Module for UART Communication (Rev. A) 06 Sep 2011
Functional safety information Leveraging the High-End Timer Transfer Unit on Hercules ARM Safety MCUs (Rev. A) 06 Sep 2011
Functional safety information Hercules™ Microcontrollers: Real-time MCUs for safety-critical products 02 Sep 2011
Application note ECC Handling in TMSx70-Based Microcontrollers 23 Feb 2011
User guide TI ICEPick Module Type C Reference Guide Public Version 17 Feb 2011
Application note NHET Getting Started (Rev. B) 30 Aug 2010
Functional safety information Generating Operating System Tick Using RTI on a Hercules ARM Safety MCU 13 Jul 2010
Functional safety information Usage of MPU Subregions on TI Hercules ARM Safety MCUs 10 Mar 2010
User guide TI Assembly Language Tools Enhanced High-End Timer (NHET) Assembler User's Guide 04 Mar 2010
White paper Discriminating between Soft Errors and Hard Errors in RAM White Paper 04 Jun 2008

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