9 Revision History
Changes from Revision F (August 2015) to Revision G (January 2024)
- 文書全体にわたって表、図、相互参照の採番方法を更新Go
- 「製品情報」表を「パッケージ情報」表に変更Go
- 「概略回路図」の JESD204B を LVDS に変更Go
Changes from Revision E (February 2013) to Revision F (August 2015)
- 「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加。Go
- 「概要」に NFBGA パッケージを追加Go
- Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device power up and initialization - RKD package.Go
- Added additional circuit configuration for unused terminalsGo
- Added additional circuit configuration for unused terminalsGo
- Added additional circuit configuration for unused terminalsGo
- Added additional circuit configuration for unused terminalsGo
- Changed DAC3484 to DAC3482 in SDENB descriptionGo
- Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device power up and initialization - ZAY package.Go
- Changed parameter name Single-Ended Swing Level to Single-Ended Input Level to better reflect the specification for minimum recommended single-ended voltage level.Go
- Changed parameter name Single-Ended Swing Level to Single-Ended Input Level to better reflect the specification for minimum recommended single-ended voltage level.Go
- Added DACCLK and OSTR minimum voltage note to Section 5.6
Go
- Added text and application report link to Section 6.3.3
Go
- Added reference to LMK0480x family in Section 6.3.3
Go
- Added pin number per package for LPF pin in Section 6.3.5.2
Go
- Changed figure and table references in Section 6.3.6
Go
- Changed first paragraph in Section 6.3.7
Go
- Deleted redundant text from Section 6.3.11.2
Go
- Changed point to pointer in Section 6.3.12
Go
- Added note to Figure 6-32
Go
- Added VCOM values to Table 6-9
Go
- Added Section 6.3.15
Go
- Added clarification on timing requirement acronyms to Section 6.4.1.2. Go
- Deleted or in Section 6.5.1 descriptionGo
- Changed P = 3 to P = 4 in Section 6.5.2.2 to reflect the correct example start-up routine configuration Go
- Added pin description for both packagesGo
- Changed Config7, bit 3 naming typo Go
- Changed config10 to config11 and 0x0A to 0x0B in register config11Go
- Changed QMC offset registers to QMC correction registers in config16 function Go
- Changed Qfine to fine in config18 function Go
- Added reference in config26 function Go
- Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device power up and initialization in config27 function Go
- Changed 1.2VDIG to DIGVDD in config27 functionGo
- Added pin description for both packages to register config35 descriptionGo
- Added reference to Digital Input Timing Specifications in register config36 descriptionGo
Changes from Revision D (August 2012) to Revision E (February 2013)
- Changed Power Supply Specification Table under Electrical Specification. This specification depends on the enhanced production test coverage and is specific to devices with certain date code. Refer to Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification Section for detailsGo
- Deleted Note (5) in Power Consumption Specification to reflect the latest DAC3482 speed specification. Go
- Changed DACCLKP/N typical clock swing specification to reflect commonly used LVPECL driverGo
- Changed DACCLKP/N typical clock swing specification to reflect commonly used LVPECL driverGo
- Changed DACCLK driver requirement to reflect actual device performance under commonly used LVPECL driversGo
- Changed Analog Output Specification Table under Electrical Specification. This specification depends on the enhanced production test coverage and is specific to devices with certain date code. Refer to Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification Section for detailsGo
- Added Phase-Locked Loop Specification Table under Electrical Specification. This specification depends on the enhanced production test coverage and is specific to devices with certain date code. Refer to Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification Section for detailsGo
- Changed Digital Latency Specification for QMC to reflect the actual
DAC3482 parameterGo
- Changed Digital Latency Specification for Inverse Sinc to reflect
the actual DAC3482 parameterGo
- Changed syncsel_fifoout(3:0) description to clarify the FIFO read pointer reset capture method and limitationGo
- Changed information to Single Sync Source Mode section to clarify the latency limitation of Single Sync Source ModeGo
- Added "the effect of bypassing the FIFO" in the Bypass Mode section to clarify the operation of FIFO, LVDS FRAME, and LVDS SYNC in FIFO Bypass ModeGo
- Changed PLL Mode section with additional operating recommendations for the DAC3482 on-chip PLLGo
- Changed Data Pattern Checker section with additional operating recommendationsGo
- Added additional requirements for Block Parity section when byte wide input data mode is selectedGo
- Changed information to Multi-Device Operation: Single Sync Source Mode section to clarify the latency limitation of Single Sync Source ModeGo
- Changed Figure 6-42 to clarify the latency limitation of Single Sync Source ModeGo
- Changed the NCO setting description in the Example Start-up Sequence Section to reflect the example register writesGo
- Changed pll_vco(6:0) to pll_vco(5:0) to reflect actual bit width in the registerGo
- Changed config45, bit12:1 default value to reflect the actual default register valueGo
- Changed config45, bit0 description to clarify additional DAC3482 behaviorGo
Changes from Revision C (June 2012) to Revision D (August 2012)
- Added thermal information to the Absolute Maximum Ratings tableGo
- Added Recommended Operating Conditions tableGo
- Deleted TJ row from top of thermal tableGo
- Deleted Operating Range section from bottom of Electrical Characteristics – DC Specifications tableGo
Changes from Revision B (September 2011) to Revision C (June 2012)
- 「特長」のパッケージ オプションを変更Go
- Added ZAY packageGo
- Added ZAY pin functionsGo
- Added ZAY package to Thermal Information sectionGo
- Added Input Common Mode max value of 1.6VGo
- Added information to CLOCK INPUT (DACCLKP/N) in Electrical Characteristics – Digital SpecificationsGo
- Added information to OUTPUT STROBE (OSTRP/N) in Electrical Characteristics – Digital SpecificationsGo
- Changed Electrical Characteristics – AC Specifications AC Performance informationGo
- Changed Figure 5-20
Go
- Changed Figure 5-21
Go
- Changed Figure 5-22
Go
- Changed Figure 5-23
Go
- Added Figure 5-47
Go
- Added Figure 5-48
Go
- Changed config3 to config9 in Section 6.3.3
Go
- Added information for double-charge-pump current to PLL MODE sectionGo
- Changed Figure 6-23
Go
- Changed +3.75 to –3.75 degrees in 1024 steps to +26.5 to –26.5 degrees in 4096 steps in Gain and Phase Correction sectionGo
Changes from Revision A (March 2011) to Revision B (September 2011)
- Changed ALARM descriptionGo
- Added notes to Electrical Characteristics – DC SpecificationsGo
- Deleted TYP and MAX values from VA,B+
Go
- Changed VCOM MIN value from 1.075V to 1.0VGo
- Added MIN and MAX values for ZT
Go
- Added fDAC PLL ON MIN of 1000MSPS in Electrical Characteristics – AC SpecificationsGo
- Added information to Single Sync Source Mode section to clarify the latency limitation of Single Sync Source ModeGo
- Changed 1.2288GHz to 983.04MHz in PLL Mode descriptionGo
- Changed data in Table 6-4
Go
- Deleted 2x in Table 6-6
Go
- Changed config32 to config 31 in Power-Up Sequence descriptionGo
- Changed Example Start-up Routine informationGo
- Changed Table 6-10
Go
- Changed config5 default value from 0x0000 to NA in Register MapGo
- Changed register version default value from 0x5409 to 0x540C in Register MapGo
- Added SIF SYNC to register config32 descriptionGo
- Changed register config35 descriptionGo
- Changed register config36 description from 40 ps to 50 psGo
- Changed register version default value from 0x5409 to 0x540CGo
Changes from Revision * (March 2011) to Revision A (March 2011)