JAJSSH9A May 2023 – January 2024 PCMD3180-Q1
PRODUCTION DATA
ADDRESS | REGISTER | DESCRIPTION | SECTION |
0x00 | PAGE_CFG | Device page register | PAGE_CFG Register (P0_R0) |
0x01 | SW_RESET | Software reset register | SW_RESET Register (P0_R1) |
0x02 | SLEEP_CFG | Sleep mode register | SLEEP_CFG Register (P0_R2) |
0x05 | SHDN_CFG | Shutdown configuration register | SHDN_CFG Register (P0_R5) |
0x07 | ASI_CFG0 | ASI configuration register 0 | ASI_CFG0 Register (P0_R7) |
0x08 | ASI_CFG1 | ASI configuration register 1 | ASI_CFG1 Register (P0_R8) |
0x09 | ASI_CFG2 | ASI configuration register 2 | ASI_CFG2 Register (P0_R9) |
0x0B | ASI_CH1 | Channel 1 ASI slot configuration register | ASI_CH1 Register (P0_R11) |
0x0C | ASI_CH2 | Channel 2 ASI slot configuration register | ASI_CH2 Register (P0_R12) |
0x0D | ASI_CH3 | Channel 3 ASI slot configuration register | ASI_CH3 Register (P0_R13) |
0x0E | ASI_CH4 | Channel 4 ASI slot configuration register | ASI_CH4 Register (P0_R14) |
0x0F | ASI_CH5 | Channel 5 ASI slot configuration register | ASI_CH5 Register (P0_R15) |
0x10 | ASI_CH6 | Channel 6 ASI slot configuration register | ASI_CH6 Register (P0_R16) |
0x11 | ASI_CH7 | Channel 7 ASI slot configuration register | ASI_CH7 Register (P0_R17) |
0x12 | ASI_CH8 | Channel 8 ASI slot configuration register | ASI_CH8 Register (P0_R18) |
0x13 | MST_CFG0 | ASI controller mode configuration register 0 | MST_CFG0 Register (P0_R19) |
0x14 | MST_CFG1 | ASI controller mode configuration register 1 | MST_CFG1 Register (P0_R20) |
0x15 | ASI_STS | ASI bus clock monitor status register | ASI_STS Register (P0_R21) |
0x16 | CLK_SRC | Clock source configuration register 0 | CLK_SRC Register (P0_R22) |
0x1F | PDMCLK_CFG | PDM clock generation configuration register | PDMCLK_CFG Register (P0_R31) |
0x20 | PDMIN_CFG | PDM DINx sampling edge register | PDMIN_CFG Register (P0_R32) |
0x21 | GPIO_CFG0 | GPIO configuration register 0 | GPIO_CFG0 Register (P0_R33) |
0x22 | GPO_CFG0 | GPO configuration register 0 | GPO_CFG0 Register (P0_R34) |
0x23 | GPO_CFG1 | GPO configuration register 1 | GPO_CFG1 Register (P0_R35) |
0x24 | GPO_CFG2 | GPO configuration register 2 | GPO_CFG2 Register (P0_R36) |
0x25 | GPO_CFG3 | GPO configuration register 3 | GPO_CFG3 Register (P0_R37) |
0x29 | GPO_VAL | GPIO, GPO output value register | GPO_VAL Register (P0_R41) |
0x2A | GPIO_MON | GPIO monitor value register | GPIO_MON Register (P0_R42) |
0x2B | GPI_CFG0 | GPI configuration register 0 | GPI_CFG0 Register (P0_R43) |
0x2C | GPI_CFG1 | GPI configuration register 1 | GPI_CFG1 Register (P0_R44) |
0x2F | GPI_MON | GPI monitor value register | GPI_MON Register (P0_R47) |
0x32 | INT_CFG | Interrupt configuration register | INT_CFG Register (P0_R50) |
0x33 | INT_MASK0 | Interrupt mask register 0 | INT_MASK0 Register (P0_R51) |
0x36 | INT_LTCH0 | Latched interrupt readback register 0 | INT_LTCH0 Register (P0_R54) |
0x3B | BIAS_CFG | MICBIAS and VREF configuration register | BIAS_CFG Register (P0_R59) |
0x3C | CH1_CFG0 | Channel 1 configuration register 0 | CH1_CFG0 Register (P0_R60) |
0x3E | CH1_CFG2 | Channel 1 configuration register 2 | CH1_CFG2 Register (P0_R62) |
0x3F | CH1_CFG3 | Channel 1 configuration register 3 | CH1_CFG3 Register (P0_R63) |
0x40 | CH1_CFG4 | Channel 1 configuration register 4 | CH1_CFG4 Register (P0_R64) |
0x41 | CH2_CFG0 | Channel 2 configuration register 0 | CH2_CFG0 Register (P0_R65) |
0x43 | CH2_CFG2 | Channel 2 configuration register 2 | CH2_CFG2 Register (P0_R67) |
0x44 | CH2_CFG3 | Channel 2 configuration register 3 | CH2_CFG3 Register (P0_R68) |
0x45 | CH2_CFG4 | Channel 2 configuration register 4 | CH2_CFG4 Register (P0_R69) |
0x46 | CH3_CFG0 | Channel 3 configuration register 0 | CH3_CFG0 Register (P0_R70) |
0x48 | CH3_CFG2 | Channel 3 configuration register 2 | CH3_CFG2 Register (P0_R72) |
0x49 | CH3_CFG3 | Channel 3 configuration register 3 | CH3_CFG3 Register (P0_R73) |
0x4A | CH3_CFG4 | Channel 3 configuration register 4 | CH3_CFG4 Register (P0_R74) |
0x4B | CH4_CFG0 | Channel 4 configuration register 0 | CH4_CFG0 Register (P0_R75) |
0x4D | CH4_CFG2 | Channel 4 configuration register 2 | CH4_CFG2 Register (P0_R77) |
0x4E | CH4_CFG3 | Channel 4 configuration register 3 | CH4_CFG3 Register (P0_R78) |
0x4F | CH4_CFG4 | Channel 4 configuration register 4 | CH4_CFG4 Register (P0_R79) |
0x50 | CH5_CFG0 | Channel 5 configuration register 0 | CH5_CFG0 Register (P0_R80) |
0x52 | CH5_CFG2 | Channel 5 configuration register 2 | CH5_CFG2 Register (P0_R82) |
0x53 | CH5_CFG3 | Channel 5 configuration register 3 | CH5_CFG3 Register (P0_R83) |
0x54 | CH5_CFG4 | Channel 5 configuration register 4 | CH5_CFG4 Register (P0_R84) |
0x55 | CH6_CFG0 | Channel 6 configuration register 0 | CH6_CFG0 Register (P0_R85) |
0x57 | CH6_CFG2 | Channel 6 configuration register 2 | CH6_CFG2 Register (P0_R87) |
0x58 | CH6_CFG3 | Channel 6 configuration register 3 | CH6_CFG3 Register (P0_R88) |
0x59 | CH6_CFG4 | Channel 6 configuration register 4 | CH6_CFG4 Register (P0_R89) |
0x5A | CH7_CFG0 | Channel 7 configuration register 0 | CH7_CFG0 Register (P0_R90) |
0x5C | CH7_CFG2 | Channel 7 configuration register 2 | CH7_CFG2 Register (P0_R92) |
0x5D | CH7_CFG3 | Channel 7 configuration register 3 | CH7_CFG3 Register (P0_R93) |
0x5E | CH7_CFG4 | Channel 7 configuration register 4 | CH7_CFG4 Register (P0_R94) |
0x5F | CH8_CFG0 | Channel 8 configuration register 0 | CH8_CFG0 Register (P0_R95) |
0x61 | CH8_CFG2 | Channel 8 configuration register 2 | CH8_CFG2 Register (P0_R97) |
0x62 | CH8_CFG3 | Channel 8 configuration register 3 | CH8_CFG3 Register (P0_R98) |
0x63 | CH8_CFG4 | Channel 8 configuration register 4 | CH8_CFG4 Register (P0_R99) |
0x6B | DSP_CFG0 | DSP configuration register 0 | DSP_CFG0 Register (P0_R107) |
0x6C | DSP_CFG1 | DSP configuration register 1 | DSP_CFG1 Register (P0_R108) |
0x73 | IN_CH_EN | Input channel enable configuration register | IN_CH_EN Register (P0_R115) |
0x74 | ASI_OUT_CH_EN | ASI output channel enable configuration register | ASI_OUT_CH_EN Register (P0_R116) |
0x75 | PWR_CFG | Power up configuration register | PWR_CFG Register (P0_R117) |
0x76 | DEV_STS0 | Device status value register 0 | DEV_STS0 Register (P0_R118) |
0x77 | DEV_STS1 | Device status value register 1 | DEV_STS1 Register (P0_R119) |
0x7E | I2C_CKSUM | I2C check sum register | I2C_CKSUM Register (P0_R126) |