JAJSDS2A September 2017 – February 2022 TIC10024-Q1
PRODUCTION DATA
Table 9-3 lists the memory-mapped registers for the TIC10024-Q1. All register offset addresses not listed in Table 9-3 should be considered as reserved locations and the register contents should not be modified.
| OFFSET | TYPE | RESET | ACRONYM | REGISTER NAME | SECTION |
|---|---|---|---|---|---|
| 1h | R | 120h | DEVICE_ID | Device ID Register | Go |
| 2h | RC | 1h | INT_STAT | Interrupt Status Register | Go |
| 3h | R | FFFFh | CRC | CRC Result Register | Go |
| 4h | R | 0h | IN_STAT_MISC | Miscellaneous Status Register | Go |
| 5h | R | 0h | IN_STAT_COMP | Comparator Status Register | Go |
| 6h-19h | — | — | RESERVED | RESERVED | — |
| 1Ah | R/W | 0h | CONFIG | Device Global Configuration Register | Go |
| 1Bh | R/W | 0h | IN_EN | Input Enable Register | Go |
| 1Ch | R/W | 0h | CS_SELECT | Current Source/Sink Selection Register | Go |
| 1Dh-1Eh | R/W | 0h | WC_CFG0, WC_CFG1 | Wetting Current Configuration Register | Go |
| 1Fh-20h | R/W | 0h | CCP_CFG0, CCP_CFG1 | Clean Current Polling Register | Go |
| 21h | R/W | 0h | THRES_COMP | Comparator Threshold Control Register | Go |
| 22h-23h | R/W | 0h | INT_EN_COMP1, INT_EN_COMP2 | Comparator Input Interrupt Generation Control Register | Go |
| 24h | R/W | 0h | INT_EN_CFG0 | Global Interrupt Generation Control Register | Go |
| 25h-32h | — | — | RESERVED | RESERVED | — |
DEVICE_ID is shown in Figure 9-3 and described in Table 9-4.
Return to Summary Table.
This register represents the device ID of the TIC10024-Q1.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
| RESERVED | |||||||||||
| R-0h | |||||||||||
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MAJOR | MINOR | |||||||||
| R-0h | R-12h | R-0h | |||||||||
| LEGEND: R = Read only |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-11 | RESERVED | R | 0h | RESERVED |
| 10-4 | MAJOR | R | 12h | These 7 bits represents major revision ID. For TIC10024-Q1 the major revision ID is 12h. |
| 3-0 | MINOR | R | 0h | These 4 bits represents minor revision ID. For TIC10024-Q1 the minor revision ID is 0h. |
INT_STAT is shown in Figure 9-4 and described in Table 9-5.
Return to Summary Table.
This register records the information of the event as it occurs in the device. A READ command executed on this register clears its content and resets the register to its default value. The INT pin is released at the rising edge of the CS pin from the READ command.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CHK_FAIL | RESERVED | CRC_CALC | ||||
| R-0h | RC-0h | R-0h | RC-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UV | OV | TW | TSD | SSC | PRTY_FAIL | SPI_FAIL | POR |
| RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-1h |
| LEGEND: R = Read only; RC = Read to clear |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-14 | RESERVED | R | 0h | RESERVED |
| 13 | CHK_FAIL | RC | 0h | 0h = Default factory setting is successfully loaded upon device initialization or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = An error is detected when loading factory settings into the device upon device initialization. During device initialization, factory settings are programmed into the device to allow proper device operation. The device performs a self-check after the device is programmed to diagnose whether correct settings are loaded. If the self-check returns an error, the CHK_FAIL bit is flagged to logic 1 along with the POR bit. The host controller is then recommended to initiate a software reset (see section Software Reset) to re-initialize the device and allow correct settings to be re-programmed. |
| 12-9 | RESERVED | R | 0h | RESERVED |
| 8 | CRC_CALC | RC | 0h | 0h = CRC calculation is running, not started, or was acknowledged after a READ command was executed on the INT_STAT register. 1h = CRC calculation is finished. CRC calculation (see section Cyclic Redundancy Check (CRC)) can be triggered to make sure correct register values are programmed into the device. Once the calculation is completed, the CRC_CALC bit is flagged to logic 1 to indicate completion of the calculation, and the result can then be accessed from the CRC (offset = 3h) register. |
| 7 | UV | RC | 0h | 0h = No under-voltage condition occurred or cleared on the VS pin, or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Under-voltage condition occurred or cleared on the VS pin. When the UV bit is flagged to logic 1, it indicates the Under-Voltage (UV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the UV operation, please refer to section VS under-voltage (UV) condition. |
| 6 | OV | RC | 0h | 0h = No over-voltage condition occurred or cleared on the VS pin, or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Over-voltage condition occurred or cleared on the VS pin. When the OV bit is flagged to logic 1, it indicates the Over-Voltage (OV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the OV operation, please refer to section VS over-voltage (OV) condition. |
| 5 | TW | RC | 0h | 0h = No temperature warning event occurred or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Temperature warning event occurred or cleared. When the TW bit is flagged to logic 1, it indicates the temperature warning event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature warning operation, please refer to section Temperature Warning (TW) |
| 4 | TSD | RC | 0h | 0h = No temperature Shutdown event occurred or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Temperature Shutdown event occurred or cleared. When the TSD bit is flagged to logic 1, it indicates the temperature shutdown event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature shutdown operation, please refer to section Temperature shutdown (TSD) |
| 3 | SSC | RC | 0h | 0h = No switch state change occurred or the status got cleared after a READ command was executed on the INT_STAT register. 1h = Switch state change occurred. The Switch State Change (SSC) bit indicates whether input threshold crossing has occurred from switch inputs IN0 to IN23. This bit is also flagged to logic 1 after the first polling cycle is completed after device polling is triggered. |
| 2 | PRTY_FAIL | RC | 0h | 0h = No parity error occurred in the last received SI stream or the error status got cleared after a READ command was executed on the INT_STAT register. 1h = Parity error occurred. When the PRTY_FAIL bit is flagged to logic 1, it indicates the last SPI responder in (SI) transaction has a parity error. The device uses odd parity. If the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. The value of this register bit is mirrored to the PRTY_FLAG SPI status flag. |
| 1 | SPI_FAIL | RC | 0h | 0h = 32 clock pulse during a CS = low sequence was detected or the error status got cleared after a READ command was executed on the INT_STAT register. 1h = SPI error occurred When the SPI_FAIL bit is flagged to logic 1, it indicates the last SPI responder in (SI) transaction is invalid. To program a complete word, 32 bits of information must be entered into the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit is flagged to logic 1, and the data received is considered invalid. The value of this register bit is mirrored to the SPI_FLAG SPI status flag. Note the SPI_FAIL bit is not flagged if SCLK is not present. |
| 0 | POR | RC | 1h | 0h = no Power-On-Reset (POR) event occurred or the status got cleared after a READ command was executed on the INT_STAT register. 1h = Power-On-Reset (POR) event occurred. The Power-On-Reset (POR) interrupt bit indicates whether a reset event has occurred. A reset event sets the registers to their default values and re-initializes the device state machine. This bit is asserted after a successful power-on-reset, hardware reset, or software reset. The value of this register bit is mirrored to the POR SPI status flag. |
CRC is shown in Figure 9-5 and described in Table 9-6.
Return to Summary Table.
This register returns the CRC-16-CCCIT calculation result. The microcontroller can compare this value with its own calculated value to ensure correct register settings are programmed to the device.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CRC | ||||||||||||||||||||||
| R-0h | R-FFFFh | ||||||||||||||||||||||
| LEGEND: R = Read only |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-16 | RESERVED | R | 0h | Reserved |
| 15-0 | CRC | R | FFFFh | CRC-16-CCITT calculation result: Bit1: LSB of CRC Bit16: MSB or CRC |
IN_STAT_MISC is shown in Figure 9-6 and described in Table 9-7.
Return to Summary Table.
This register indicates current device status unrelated to switch input monitoring.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | UV_STAT | OV_STAT | TW_STAT | TSD_STAT | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-4 | RESERVED | R | 0h | Reserved |
| 3 | UV_STAT | R | 0h | 0h = VS voltage is above the under-voltage condition threshold. 1h = VS voltage is below the under-voltage condition threshold. |
| 2 | OV_STAT | R | 0h | 0h = VS voltage is below the over-voltage condition threshold. 1h = VS voltage is above the over-voltage condition threshold. |
| 1 | TW_STAT | R | 0h | 0h = Device junction temperature is below the temperature warning threshold TTW. 1h = Device junction temperature is above the temperature warning threshold TTW. |
| 0 | TSD_STAT | R | 0h | 0h = Device junction temperature is below the temperature shutdown threshold TTSD. 1h = Device junction temperature is above the temperature shutdown threshold TTSD. |
IN_STAT_COMP is shown in Figure 9-7 and described in Table 9-8.
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This register indicates whether an input is below or above the comparator threshold.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| INC_23 | INC_22 | INC_21 | INC_20 | INC_19 | INC_18 | INC_17 | INC_16 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| INC_15 | INC_14 | INC_13 | INC_12 | INC_11 | INC_10 | INC_9 | INC_8 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INC_7 | INC_6 | INC_5 | INC_4 | INC_3 | INC_2 | INC_1 | INC_0 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| LEGEND: R = Read only |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | INC_23 | R | 0h | 0h = Input IN23 is below the comparator threshold. 1h = Input IN23 is above the comparator threshold. |
| 22 | INC_22 | R | 0h | 0h = Input IN22 is below the comparator threshold. 1h = Input IN22 is above the comparator threshold. |
| 21 | INC_21 | R | 0h | 0h = Input IN21 is below the comparator threshold. 1h = Input IN21 is above the comparator threshold. |
| 20 | INC_20 | R | 0h | 0h = Input IN20 is below the comparator threshold. 1h = Input IN20 is above the comparator threshold. |
| 19 | INC_19 | R | 0h | 0h = Input IN19 is below the comparator threshold. 1h = Input IN19 is above the comparator threshold. |
| 18 | INC_18 | R | 0h | 0h = Input IN18 is below the comparator threshold. 1h = Input IN18 is above the comparator threshold. |
| 17 | INC_17 | R | 0h | 0h = Input IN17 is below the comparator threshold. 1h = Input IN17 is above the comparator threshold. |
| 16 | INC_16 | R | 0h | 0h = Input IN16 is below the comparator threshold. 1h = Input IN16 is above the comparator threshold. |
| 15 | INC_15 | R | 0h | 0h = Input IN15 is below the comparator threshold. 1h = Input IN15 is above the comparator threshold. |
| 14 | INC_14 | R | 0h | 0h = Input IN14 is below the comparator threshold. 1h = Input IN14 is above the comparator threshold. |
| 13 | INC_13 | R | 0h | 0h = Input IN13 is below the comparator threshold. 1h = Input IN13 is above the comparator threshold. |
| 12 | INC_12 | R | 0h | 0h = Input IN12 is below the comparator threshold. 1h = Input IN12 is above the comparator threshold. |
| 11 | INC_11 | R | 0h | 0h = Input IN11 is below the comparator threshold. 1h = Input IN11 is above the comparator threshold. |
| 10 | INC_10 | R | 0h | 0h = Input IN10 is below the comparator threshold. 1h = Input IN10 is above the comparator threshold. |
| 9 | INC_9 | R | 0h | 0h = Input IN9 is below the comparator threshold. 1h = Input IN9 is above the comparator threshold. |
| 8 | INC_8 | R | 0h | 0h = Input IN8 is below the comparator threshold. 1h = Input IN8 is above the comparator threshold. |
| 7 | INC_7 | R | 0h | 0h = Input IN7 is below the comparator threshold. 1h = Input IN7 is above the comparator threshold. |
| 6 | INC_6 | R | 0h | 0h = Input IN6 is below the comparator threshold. 1h = Input IN6 is above the comparator threshold. |
| 5 | INC_5 | R | 0h | 0h = Input IN5 is below the comparator threshold. 1h = Input IN5 is above the comparator threshold. |
| 4 | INC_4 | R | 0h | 0h = Input IN4 is below the comparator threshold. 1h = Input IN4 is above the comparator threshold. |
| 3 | INC_3 | R | 0h | 0h = Input IN3 is below the comparator threshold. 1h = Input IN3 is above the comparator threshold. |
| 2 | INC_2 | R | 0h | 0h = Input IN2 is below the comparator threshold. 1h = Input IN2 is above the comparator threshold. |
| 1 | INC_1 | R | 0h | 0h = Input IN1 is below the comparator threshold. 1h = Input IN1 is above the comparator threshold. |
| 0 | INC_0 | R | 0h | 0h = Input IN0 is below the comparator threshold. 1h = Input IN0 is above the comparator threshold. |
CONFIG is shown in Figure 9-8 and described in Table 9-9.
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| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | TW_CUR_DIS_CSI | ||||||
| R-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DET_FILTER | TW_CUR_DIS_CSO | INT_CONFIG | TRIGGER | POLL_EN | CRC_T | POLL_ACT_TIME | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| POLL_ACT_TIME | POLL_TIME | RESET | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| LEGEND: R/W = Read/Write |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-17 | RESERVED | R | 0h | Reserved |
| 16 | TW_CUR_DIS_CSI | R/W | 0h | 0h = Enable wetting current reduction (to 2 mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSI. 1h = Disable wetting current reduction (to 2 mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSI. |
| 15-14 | DET_FILTER | R/W | 0h | For detailed descriptions for the detection filter, refer to section Detection Filter. 0h = every sample is valid and taken for threshold evaluation 1h = 2 consecutive and equal samples required to be valid data 2h = 3 consecutive and equal samples required to be valid data 3h = 4 consecutive and equal samples required to be valid data |
| 13 | TW_CUR_DIS_CSO | R/W | 0h | 0h = Enable wetting current reduction (to 2mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSO. 1h = Disable wetting current reduction (to 2mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSO. |
| 12 | INT_CONFIG | R/W | 0h | For detailed descriptions for the INT pin assertion scheme, refer to section Interrupt Generation and /INT Assertion. 0h = INT pin assertion scheme set to static 1h = INT pin assertion scheme set to dynamic |
| 11 | TRIGGER | R/W | 0h | When the TRIGGER bit is set to logic 1, normal device operation (wetting current activation and polling) starts. To stop device operation and keep the device in an idle state, de-assert this bit to 0. After device normal operation is triggered, if at any time the device setting needs to be re-configured, the microcontroller is required to first set the bit TRIGGER to logic 0 to stop device operation. Once the re-configuration is completed, the microcontroller can set the TRIGGER bit back to logic 1 to re-start device operation. If re-configuration is done on the fly without first stopping the device operation, false switch status could be reported and accidental interrupt might be issued. The following register bits are the exception and can be configured when TRIGGER bit is set to logic 1: – TRIGGER (bit 11 of the CONFIG register) – CRC_T (bit 9 of the CONFIG register) – RESET (bit 0 of the CONFIG register) – The CCP_CFG1 register 0h = Stop TIC10024-Q1 from normal operation. 1h = Trigger TIC10024-Q1 normal operation |
| 10 | POLL_EN | R/W | 0h | 0h = Polling disabled. Device operates in continuous mode. 1h = Polling enabled and the device operates in one of the polling modes. |
| 9 | CRC_T | R/W | 0h | Set this bit to 1 to trigger a CRC calculation on all the configuration register bits. Once triggered, it is strongly recommended the SPI commander does not change the content of the configuration registers until the CRC calculation is completed to avoid erroneous CRC calculation result. The TIC10024-Q1 sets the CRC_CALC interrupt bit and asserts the INT pin low when the CRC calculation is completed. The calculated result will be available in the CRC register. This bit self-clears back to 0 after CRC calculation is executed. 0h = no CRC calculation triggered 1h = trigger CRC calculation |
| 8-5 | POLL_ACT_TIME | R/W | 0h | 0h = 64μs 1h = 128μs 2h = 192μs 3h = 256μs 4h = 320μs 5h = 384μs 6h = 448μs 7h = 512μs 8h = 640μs 9h = 768μs Ah = 896μs Bh = 1024μs Ch = 2048μs Dh-15h = 512μs (most frequently-used setting) |
| 4-1 | POLL_TIME | R/W | 0h | 0h = 2ms 1h = 4ms 2h = 8ms 3h = 16ms 4h = 32ms 5h = 48ms 6h = 64ms 7h = 128ms 8h = 256ms 9h = 512ms Ah = 1024ms Bh = 2048ms Ch = 4096ms Dh-15h = 8ms (most frequently-used setting) |
| 0 | RESET | R/W | 0h | 0h = No reset 1h = Trigger software reset of the device. |
IN_EN is shown in Figure 9-9 and described in Table 9-10.
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| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| IN_EN_23 | IN_EN_22 | IN_EN_21 | IN_EN_20 | IN_EN_19 | IN_EN_18 | IN_EN_17 | IN_EN_16 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IN_EN_15 | IN_EN_14 | IN_EN_13 | IN_EN_12 | IN_EN_11 | IN_EN_10 | IN_EN_9 | IN_EN_8 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IN_EN_7 | IN_EN_6 | IN_EN_5 | IN_EN_4 | IN_EN_3 | IN_EN_2 | IN_EN_1 | IN_EN_0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| LEGEND: R/W = Read/Write |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | IN_EN_23 | R/W | 0h | 0h = Input channel IN23 disabled. Polling sequence skips this channel 1h = Input channel IN23 enabled. |
| 22 | IN_EN_22 | R/W | 0h | 0h = Input channel IN22 disabled. Polling sequence skips this channel 1h = Input channel IN22 enabled. |
| 21 | IN_EN_21 | R/W | 0h | 0h = Input channel IN21 disabled. Polling sequence skips this channel 1h = Input channel IN21 enabled. |
| 20 | IN_EN_20 | R/W | 0h | 0h = Input channel IN20 disabled. Polling sequence skips this channel 1h = Input channel IN20 enabled. |
| 19 | IN_EN_19 | R/W | 0h | 0h = Input channel IN19 disabled. Polling sequence skips this channel 1h = Input channel IN19 enabled. |
| 18 | IN_EN_18 | R/W | 0h | 0h = Input channel IN18 disabled. Polling sequence skips this channel 1h = Input channel IN18 enabled. |
| 17 | IN_EN_17 | R/W | 0h | 0h = Input channel IN17 disabled. Polling sequence skips this channel 1h = Input channel IN17 enabled. |
| 16 | IN_EN_16 | R/W | 0h | 0h = Input channel IN16 disabled. Polling sequence skips this channel 1h = Input channel IN16 enabled. |
| 15 | IN_EN_15 | R/W | 0h | 0h = Input channel IN15 disabled. Polling sequence skips this channel 1h = Input channel IN15 enabled. |
| 14 | IN_EN_14 | R/W | 0h | 0h = Input channel IN14 disabled. Polling sequence skips this channel 1h = Input channel IN14 enabled. |
| 13 | IN_EN_13 | R/W | 0h | 0h = Input channel IN13 disabled. Polling sequence skips this channel 1h = Input channel IN13 enabled. |
| 12 | IN_EN_12 | R/W | 0h | 0h = Input channel IN12 disabled. Polling sequence skips this channel 1h = Input channel IN12 enabled. |
| 11 | IN_EN_11 | R/W | 0h | 0h = Input channel IN11 disabled. Polling sequence skips this channel 1h = Input channel IN11 enabled. |
| 10 | IN_EN_10 | R/W | 0h | 0h = Input channel IN10 disabled. Polling sequence skips this channel 1h = Input channel IN10 enabled. |
| 9 | IN_EN_9 | R/W | 0h | 0h = Input channel IN9 disabled. Polling sequence skips this channel 1h = Input channel IN9 enabled. |
| 8 | IN_EN_8 | R/W | 0h | 0h = Input channel IN8 disabled. Polling sequence skips this channel 1h = Input channel IN8 enabled. |
| 7 | IN_EN_7 | R/W | 0h | 0h = Input channel IN7 disabled. Polling sequence skips this channel 1h = Input channel IN7 enabled. |
| 6 | IN_EN_6 | R/W | 0h | 0h = Input channel IN6 disabled. Polling sequence skips this channel 1h = Input channel IN6 enabled. |
| 5 | IN_EN_5 | R/W | 0h | 0h = Input channel IN5 disabled. Polling sequence skips this channel 1h = Input channel IN5 enabled. |
| 4 | IN_EN_4 | R/W | 0h | 0h = Input channel IN4 disabled. Polling sequence skips this channel 1h = Input channel IN4 enabled. |
| 3 | IN_EN_3 | R/W | 0h | 0h = Input channel IN3 disabled. Polling sequence skips this channel 1h = Input channel IN3 enabled. |
| 2 | IN_EN_2 | R/W | 0h | 0h = Input channel IN2 disabled. Polling sequence skips this channel 1h = Input channel IN2 enabled. |
| 1 | IN_EN_1 | R/W | 0h | 0h = Input channel IN1 disabled. Polling sequence skips this channel 1h = Input channel IN1 enabled. |
| 0 | IN_EN_0 | R/W | 0h | 0h = Input channel IN0 disabled. Polling sequence skips this channel 1h = Input channel IN0 enabled. |
CS_SELECT is shown in Figure 9-10 and described in Table 9-11.
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| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
| RESERVED | |||||||||||
| R-0h | |||||||||||
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CS_IN9 | CS_IN8 | CS_IN7 | CS_IN6 | CS_IN5 | CS_IN4 | CS_IN3 | CS_IN2 | CS_IN1 | CS_IN0 | |
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-10 | RESERVED | R | 0h | Reserved |
| 9 | CS_IN9 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
| 8 | CS_IN8 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
| 7 | CS_IN7 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
| 6 | CS_IN6 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
| 5 | CS_IN5 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
| 4 | CS_IN4 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
| 3 | CS_IN3 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
| 2 | CS_IN2 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
| 1 | CS_IN1 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
| 0 | CS_IN0 | R/W | 0h | 0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected |
WC_CFG0 is shown in Figure 9-11 and described in Table 9-12.
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| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
| WC_IN11 | WC_IN10 | WC_IN8_IN9 | WC_IN6_IN7 | ||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WC_IN5 | WC_IN4 | WC_IN2_IN3 | WC_IN0_IN1 | ||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
| LEGEND: R/W = Read/Write |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-21 | WC_IN11 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 20-18 | WC_IN10 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 17-15 | WC_IN8_IN9 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 14-12 | WC_IN6_IN7 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 11-9 | WC_IN5 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 8-6 | WC_IN4 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 5-3 | WC_IN2_IN3 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 2-0 | WC_IN0_IN1 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
WC_CFG1 is shown in Figure 9-12 and described in Table 9-13.
Return to Summary Table.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
| RESERVED | AUTO_SCALE_DIS_CSI | AUTO_SCALE_DIS_CSO | WC_IN23 | WC_IN22 | WC_IN20_IN21 | ||||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WC_IN18_IN19 | WC_IN16_IN17 | WC_IN14_IN15 | WC_IN12_IN13 | ||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | RESERVED | R | 0h | Reserved |
| 22 | AUTO_SCALE_DIS_CSI | R/W | 0h | 0h = Enable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CSI 1h = Disable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CS For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling. |
| 21 | AUTO_SCALE_DIS_CSO | R/W | 0h | 0h = Enable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CSO 1h = Disable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CSO For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling. |
| 20-18 | WC_IN23 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 17-15 | WC_IN22 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 14-12 | WC_IN20_IN21 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 11-9 | WC_IN18_IN19 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 8-6 | WC_IN16_IN17 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 5-3 | WC_IN14_IN15 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
| 2-0 | WC_IN12_IN13 | R/W | 0h | 0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
CCP_CFG0 is shown in Figure 9-13 and described in Table 9-14.
Return to Summary Table.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
| RESERVED | |||||||||||
| R-0h | |||||||||||
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CCP_TIME | WC_CCP3 | WC_CCP2 | WC_CCP1 | WC_CCP0 | ||||||
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-7 | RESERVED | R | 0h | Reserved |
| 6-4 | CCP_TIME | R/W | 0h | Wetting current activation time in CCP mode 0h = 64μs 1h = 128μs 2h = 192μs 3h = 256μs 4h = 320μs 5h = 384μs 6h = 448μs 7h = 512μs |
| 3 | WC_CCP3 | R/W | 0h | Wetting current setting for IN18 to IN23 in CCP mode 0h = 10mA (typ.) wetting current 1h = 15mA (typ.) wetting current |
| 2 | WC_CCP2 | R/W | 0h | Wetting current setting for IN12 to IN17 in CCP mode 0h = 10mA (typ.) wetting current 1h = 15mA (typ.) wetting current |
| 1 | WC_CCP1 | R/W | 0h | Wetting current setting for IN6 to IN11 in CCP mode 0h = 10mA (typ.) wetting current 1h = 15mA (typ.) wetting current |
| 0 | WC_CCP0 | R/W | 0h | Wetting current setting for IN0 to IN5 in CCP mode 0h = 10mA (typ.) wetting current 1h = 15mA (typ.) wetting current |
CCP_CFG1 is shown in Figure 9-14 and described in Table 9-15.
Return to Summary Table.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CCP_IN23 | CCP_IN22 | CCP_IN21 | CCP_IN20 | CCP_IN19 | CCP_IN18 | CCP_IN17 | CCP_IN16 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CCP_IN15 | CCP_IN14 | CCP_IN13 | CCP_IN12 | CCP_IN11 | CCP_IN10 | CCP_IN9 | CCP_IN8 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCP_IN7 | CCP_IN6 | CCP_IN5 | CCP_IN4 | CCP_IN3 | CCP_IN2 | CCP_IN1 | CCP_IN0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| LEGEND: R/W = Read/Write |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | CCP_IN23 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 22 | CCP_IN22 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 21 | CCP_IN21 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 20 | CCP_IN20 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 19 | CCP_IN19 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 18 | CCP_IN18 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 17 | CCP_IN17 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 16 | CCP_IN16 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 15 | CCP_IN15 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 14 | CCP_IN14 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 13 | CCP_IN13 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 12 | CCP_IN12 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 11 | CCP_IN11 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 10 | CCP_IN10 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 9 | CCP_IN9 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 8 | CCP_IN8 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 7 | CCP_IN7 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 6 | CCP_IN6 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 5 | CCP_IN5 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 4 | CCP_IN4 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 3 | CCP_IN3 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 2 | CCP_IN2 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 1 | CCP_IN1 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
| 0 | CCP_IN0 | R/W | 0h | 0h = no CCP wetting current 1h = CCP wetting current activated |
THRES_COMP is shown in Figure 9-15 and described in Table 9-16.
Return to Summary Table.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | THRES_COMP_IN20_IN23 | THRES_COMP_IN16_IN19 | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| THRES_COMP_IN12_IN15 | THRES_COMP_IN8_IN11 | THRES_COMP_IN4_IN7 | THRES_COMP_IN0_IN3 | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-12 | RESERVED | R | 0h | Reserved |
| 11-10 | THRES_COMP_IN20_IN23 | R/W | 0h | These 2 bits configures the comparator thresholds for input channels IN20 to IN23 0h = comparator threshold set to 2V 1h = comparator threshold set to 2.7V 2h = comparator threshold set to 3V 3h = comparator threshold set to 4V |
| 9-8 | THRES_COMP_IN16_IN19 | R/W | 0h | These 2 bits configures the comparator thresholds for input channels IN16 to IN19 0h = comparator threshold set to 2V 1h = comparator threshold set to 2.7V 2h = comparator threshold set to 3V 3h = comparator threshold set to 4V |
| 7-6 | THRES_COMP_IN12_IN15 | R/W | 0h | These 2 bits configures the comparator thresholds for input channels IN12 to IN15 0h = comparator threshold set to 2V 1h = comparator threshold set to 2.7V 2h = comparator threshold set to 3V 3h = comparator threshold set to 4V |
| 5-4 | THRES_COMP_IN8_IN11 | R/W | 0h | These 2 bits configures the comparator thresholds for input channels IN8 to IN11 0h = comparator threshold set to 2V 1h = comparator threshold set to 2.7V 2h = comparator threshold set to 3V 3h = comparator threshold set to 4V |
| 3-2 | THRES_COMP_IN4_IN7 | R/W | 0h | These 2 bits configures the comparator thresholds for input channels IN4 to IN7 0h = comparator threshold set to 2V 1h = comparator threshold set to 2.7V 2h = comparator threshold set to 3V 3h = comparator threshold set to 4V |
| 1-0 | THRES_COMP_IN0_IN3 | R/W | 0h | These 2 bits configures the comparator thresholds for input channels IN0 to IN3 0h = comparator threshold set to 2V 1h = comparator threshold set to 2.7V 2h = comparator threshold set to 3V 3h = comparator threshold set to 4V |
INT_EN_COMP1 is shown in Figure 9-16 and described in Table 9-17.
Return to Summary Table.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
| INC_EN_11 | INC_EN_10 | INC_EN_9 | INC_EN_8 | INC_EN_7 | INC_EN_6 | ||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INC_EN_5 | INC_EN_4 | INC_EN_3 | INC_EN_2 | INC_EN_1 | INC_EN_0 | ||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||
| LEGEND: R/W = Read/Write |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-22 | INC_EN_11 | R/W | 0h | 0h = no interrupt generation for IN11 1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN11 2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN11 3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN11 |
| 21-20 | INC_EN_10 | R/W | 0h | 0h = no interrupt generation for IN10 1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN10 2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN10 3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN10 |
| 19-18 | INC_EN_9 | R/W | 0h | 0h = no interrupt generation for IN9 1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN9 2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN9 3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN9 |
| 17-16 | INC_EN_8 | R/W | 0h | 0h = no interrupt generation for IN8 1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN8 2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN8 3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN8 |
| 15-14 | INC_EN_7 | R/W | 0h | 0h = no interrupt generation for IN7 1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN7 2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN7 3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN7 |
| 13-12 | INC_EN_6 | R/W | 0h | 0h = no interrupt generation for IN6 1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN6 2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN6 3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN6 |
| 11-10 | INC_EN_5 | R/W | 0h | 0h = no interrupt generation for IN5 1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN5 2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN5 3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN5 |
| 9-8 | INC_EN_4 | R/W | 0h | 0h = no interrupt generation for IN4 1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN4 2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN4 3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN4 |
| 7-6 | INC_EN_3 | R/W | 0h | 0h = no interrupt generation for IN3 1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN3 2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN3 3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN3 |
| 5-4 | INC_EN_2 | R/W | 0h | 0h = no interrupt generation for IN2 1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN2 2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN2 3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN2 |
| 3-2 | INC_EN_1 | R/W | 0h | 0h = no interrupt generation for IN1 1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN1 2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN1 3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN1 |
| 1-0 | INC_EN_0 | R/W | 0h | 0h = no interrupt generation for IN0 1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN0 2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN0 3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN0 |
INT_EN_COMP2 is shown in Figure 9-17 and described in Table 9-18.
Return to Summary Table.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
| INC_EN_23 | INC_EN_22 | INC_EN_21 | INC_EN_20 | INC_EN_19 | INC_EN_18 | ||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INC_EN_17 | INC_EN_16 | INC_EN_15 | INC_EN_14 | INC_EN_13 | INC_EN_12 | ||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||
| LEGEND: R/W = Read/Write |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-22 | INC_EN_23 | R/W | 0h | 0h = no interrupt generation for IN23 1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN23 2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN23 3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN23 |
| 21-20 | INC_EN_22 | R/W | 0h | 0h = no interrupt generation for IN22 1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN22 2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN22 3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN22 |
| 19-18 | INC_EN_21 | R/W | 0h | 0h = no interrupt generation for IN21 1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN21 2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN21 3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN21 |
| 17-16 | INC_EN_20 | R/W | 0h | 0h = no interrupt generation for IN20 1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN20 2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN20 3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN20 |
| 15-14 | INC_EN_19 | R/W | 0h | 0h = no interrupt generation for IN19 1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN19 2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN19 3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN19 |
| 13-12 | INC_EN_18 | R/W | 0h | 0h = no interrupt generation for IN18 1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN18 2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN18 3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN18 |
| 11-10 | INC_EN_17 | R/W | 0h | 0h = no interrupt generation for IN17 1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN17 2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN17 3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN17 |
| 9-8 | INC_EN_16 | R/W | 0h | 0h = no interrupt generation for IN16 1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN16 2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN16 3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN16 |
| 7-6 | INC_EN_15 | R/W | 0h | 0h = no interrupt generation for IN15 1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN15 2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN15 3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN15 |
| 5-4 | INC_EN_14 | R/W | 0h | 0h = no interrupt generation for IN14 1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN14 2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN14 3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN14 |
| 3-2 | INC_EN_13 | R/W | 0h | 0h = no interrupt generation for IN13 1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN13 2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN13 3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN13 |
| 1-0 | INC_EN_12 | R/W | 0h | 0h = no interrupt generation for IN12 1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN12 2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN12 3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN12 |
INT_EN_CFG0 is shown in Figure 9-18 and described in Table 9-19.
Return to Summary Table.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CRC_CALC_EN | UV_EN | OV_EN | TW_EN | TSD_EN | SSC_EN | PRTY_FAIL_EN | SPI_FAIL_EN |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-8 | RESERVED | R | 0h | Reserved |
| 7 | CRC_CALC_EN | R/W | 0h | 0h = INT pin assertion due to CRC calculation completion disabled. 1h = INT pin assertion due to CRC calculation completion enabled. |
| 6 | UV_EN | R/W | 0h | 0h = INT pin assertion due to UV event disabled. 1h = INT pin assertion due to UV event enabled. |
| 5 | OV_EN | R/W | 0h | 0h = INT pin assertion due to OV event disabled. 1h = INT pin assertion due to OV event enabled. |
| 4 | TW_EN | R/W | 0h | 0h = INT pin assertion due to TW event disabled. 1h = INT pin assertion due to TW event enabled. |
| 3 | TSD_EN | R/W | 0h | 0h = INT pin assertion due to TSD event disabled. 1h = INT pin assertion due to TSD event enabled. |
| 2 | SSC_EN | R/W | 0h | 0h = INT pin assertion due to SSC event disabled. 1h = INT pin assertion due to SSC event enabled. |
| 1 | PRTY_FAIL_EN | R/W | 0h | 0h = INT pin assertion due to parity fail event disabled. 1h = INT pin assertion due to parity fail event enabled. |
| 0 | SPI_FAIL_EN | R/W | 0h | 0h = INT pin assertion due to SPI fail event disabled. 1h = INT pin assertion due to SPI fail event enabled. |