JAJSF78L June   2006  – May 2018 TPS65023 , TPS65023B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 7.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 7.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 7.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 7.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 7.11 I2C Timing Requirements for TPS65023B
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 8.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 8.3.3  Power Save Mode Operation
      4. 8.3.4  Low Ripple Mode
      5. 8.3.5  Soft-Start
      6. 8.3.6  100% Duty Cycle Low Dropout Operation
      7. 8.3.7  Active Discharge When Disabled
      8. 8.3.8  Power-Good Monitoring
      9. 8.3.9  Low-Dropout Voltage Regulators
      10. 8.3.10 Undervoltage Lockout
      11. 8.3.11 Power-Up Sequencing
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 System Reset + Control Signals
        1. 8.5.1.1 DEFLDO1 and DEFLDO2
        2. 8.5.1.2 Interrupt Management and the INT Pin
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register Address: 00h (Read Only)
      2. 8.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 8.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 8.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 8.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
      6. 8.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 8.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 8.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 8.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Voltage Connection
      2. 9.1.2 Unused Regulators
      3. 9.1.3 Reset Condition of DCDC1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for Supply Voltages Below 3.0 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSB|40
サーマルパッド・メカニカル・データ
発注情報

4 改訂履歴

Changes from K Revision (December 2015) to L Revision

  • Changed データシートのタイトルGo
  • Replaced references of TI PowerPAD IC package with thermal pad Go
  • Added 「デバイス・サポート」および「ドキュメントのサポート」セクションをGo
  • Changed 「静電放電についての注意事項」の記述Go

Changes from J Revision (September 2011) to K Revision

  • Added 「ESD定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションGo

Changes from I Revision (July 2010) to J Revision

  • Added Thermal Information Table and deleted Dissipation Ratings TableGo

Changes from H Revision (December 2009) to I Revision

  • Added I2C互換のシリアル・インターフェイスを「特長」の一覧にGo
  • Added TPS65023Bのデバイス仕様Go
  • TPS65023Bデバイスの注文情報を追加Go
  • Added specs for TPS65023B deviceGo
  • Changed "VBACKUP threshold" test condition typographical error from "VBACKUP falling" to "VBACKUP rising"Go
  • Added specs for TPS65023B deviceGo
  • Added Differences table for TPS65023 and TPS65023B devicesGo

Changes from G Revision (October 2008) to H Revision

  • Changed IO(DCDC1) MAX from: 1500 mA to: 1700 mAGo
  • Added High level input voltage for the SDAT pinGo
  • Changed IO from:1500 mA MIN to 1700 mA Go
  • Changed IO maximum from:1.5 A to: 1.7 A for VDCDC1 fixed and adjustable output voltage test condition specs.Go
  • Changed IO maximum from: 1500 mA to: 1700 mA for VDCDC1 Load Regulation test conditionGo
  • Changed VDCDC1 "soft-start ramp time" spec to: "tStart and tRamp" specifications with MIN TYP MAX values.Go
  • Changed VDCDC2 "soft-start ramp time" spec To: "tStart and tRamp" specifications with MIN TYP MAX values.Go
  • Changed VDCDC3 "soft-start ramp time" spec To: "tStart and tRamp" specifications with MIN TYP MAX values.Go
  • Changed FBD graphic to show 1700 mA for DCDC1 Buck ConverterGo
  • Changed text string from: "1.2 V or 1.8 V" to: "1.2 V to 1.6 V" in the STEP-DOWN CONVERTERS.,VDCDC1.... description.Go
  • Changed graphic entity to the one used in the Application Note SLVA273Go

Changes from F Revision (July 2007) to G Revision

  • Changed the Interrupt Management and the INT Pin section.Go

Changes from E Revision (January 2007) to F Revision

  • Changed text string from: "If it is tied to VCC, the default is 2.5 V" To: "If it is tied to VCC, the default is 3.3 V"Go

Changes from D Revision (December 2006) to E Revision

  • Changed LDO1 output voltage range from: 3.3 to: 3.3Go
  • Changed text string from: "VDCDC2 converter defaults to 1.8 V or 2.5 V" to: "VDCDC2 converter defaults to 1.8 V or 3.3 V"Go

Changes from C Revision (October 2006) to D Revision

  • Changed Typical Configuration for Ti DaVinci ProcessorsGo

Changes from B Revision (June 2006) to C Revision

Changes from A Revision (June 2006) to B Revision

  • Changed 「1.5A、97%効率の降圧」から「1.7A、90%効率の降圧」にGo
  • Changed 「6mm×6mmのQFNパッケージ」から「5mm×5mmのQFNパッケージ」にGo
  • Changed RHAパッケージからRSBパッケージにGo
  • Changed from:O(DCDC2) to: IO(DCDC1)Go
  • Changed Forward current limit - removed TBD and added valuesGo
  • Changed Fixed output voltage - removed TBD and added valuesGo
  • Changed Fixed output voltage - removed TBD and added valuesGo
  • Added VINDCDC3 = 3.6 V to Maximum output currentGo
  • Changed Fixed output voltage - removed TBD and added valuesGo
  • Changed Figure 3 (DVS Timing)Go
  • Changed Figure 11 (Graph - DCDC2: OUTPUT VOLTAGE)Go
  • Added Figure 12 (Graph - DCDC3: OUTPUT VOLTAGE )Go
  • Changed Figure 20 (Graph - VDCDC2 OUTPUT VOLTAGE RIPPLE)Go
  • Added Reset Condition of DCDC1 InformationGo
  • Changed Typical Configuration for Ti DaVinci ProcessorsGo
  • Changed from: TPS65023 typically use a 3.3 μH output inductor to: TPS65023 typically use a 2.2 μH output inductorGo
  • Changed from: VDCDC3 to: VDCDC1Go
  • Changed from: VDEFDCDC3 to: DEFDCDC1Go
  • Changed from: 2.5 V to 3.3 V (Table 20)Go

Changes from * Revision (May 2006) to A Revision

  • Changed Electrical Characteristics: VDCDC1 Step-Down ConverterGo
  • Changed Electrical Characteristics: VDCDC3 Step-Down Converter Go
  • Changed CON_CTRL Register Address - Column B0 default value changed from 1 to 0.Go
  • Changed VDCDC# to VDCDC1Go