Table 8. Design Requirements

DESIGN PARAMETER	TARGET VALUE
Output voltage	19.5 V
Rated (continuous) output power	65 W
Peak (transient) output power	130 W
Peak (transient) output power duration	2 ms
Input AC voltage range	88 VRMS to 264 VRMS
Typical efficiency	88%
Minimum bulk voltage at 88 VAC/47 Hz and rated (continuous) output power	82 V

9.2.4.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the UCC2863x device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.4.2 Input Bulk Capacitance and Minimum Bulk Voltage

The required bulk capacitance value depends on the target minimum bulk capacitor ripple voltage at minimum AC input line, minimum line frequency and on the power level of interest. As a way of estimating, use 1.5-μF to 2-μF per Watt of rated, continuous power to achieve approximately 70 V to 80 V minimum at 88 V_RMS input. This case indicates a required bulk capacitance of between approximately 100 μF and 130 μF. Alternatively, the required capacitance may be explicitly calculated for a specific set of requirements using Equation 21.

Using the parameters in Table 8, this calculates a required C_BULK of 130 μF.

To help reduce differential mode (DM) emissions for conducted EMC compliance, the bulk capacitance has been split into two separate capacitors C5 and C7 in Figure 44, with a small DM choke L2 inserted between the capacitors. The total resulting capacitance of 127 μF is close to the required minimum requirement per Equation 21, and the design results in a small decrease in the actual bulk capacitor minimum ripple voltage.

Next, verify that the choice of bulk capacitance satisfies the X-capacitor discharge constraints for rate of discharge by the load when X-capacitor sampling is inactive, per Equation 5. The bulk capacitance should be less than the value calculated by Equation 22.

9.2.4.3 Transformer Turn Ratio

Choose the transformer primary-to-secondary-side turns ratio based on the allowed voltage stress for the output rectifier, or the primary MOSFET. For 19.5-V charger designs, it is valid to choose a turns ratio that allows the use of a more efficient 100-V Schottky rectifier.

For a good Schottky diode with 100-V reverse rating, V_REV(rated), the rectifier forward voltage drop, V_RECT, can be expected to be in the range of 0.4 V to 0.5 V at 3 A to 5 A, at practical operating temperatures in the region of 100°C. Allowing an 85% derating on the rectifier reverse voltage stress, Equation 23 indicates a required turns ratio of 5.734 for a maximum AC peak voltage of 373 V (264 V_RMS).

Choose the bias winding turns ratio to set the nominal bias voltage for the device VDD pin. Use an initial V_BIAS(target) of 12 V.

For a typical 0.7-V bias-diode drop, this equation calculates to 0.6366.

When the transformer size and type are chosen, the actual turns values can be calculated. Because the turns need to be rounded to integer values, the actual turns ratios achieved deviates from these targets. Check the final ratios to ensure that the secondary-side Schottky rectifier stress and the bias winding nominal level are acceptable. Adjust the specific turns counts to meet the target ratios.

9.2.4.4 Transformer Magnetizing Inductance

Match the power stage design to the modulator curves by ensuring that the boundary conduction mode (BCM – boundary of operation between DCM and CCM) point coincides with the minimum bulk-capacitor voltage at minimum line, at rated output power. This choice results in DCM operation at all line voltages for all loads up to continuous rated load, and minimizes power loss and EMC impacts due to output rectifier reverse recovery during CCM operation. This design choice allows operation to extend into the CCM region of operation as required to deliver the transient peak load.

To achieve this design target, the required primary magnetizing inductance, L_PRI is calculated from Equation 25. In this equation, the value of F_SW(nom) is 60 kHz, taken from the modulator curve region P₃ to P₄, in Table 6. The value of V_BULK(min) is the value that occurs with the actual used bulk capacitance of 127 μF.

This calculates a value of 257 μH. Round the value to 260 μH.

9.2.4.5 Current Sense Resistor R_CS

In addition to choosing L_PRI value to map the rated power to the target BCM point at minimum bulk voltage, choose the R_CS value according to Equation 26. This calculation ensures that the resulting peak current, in conjunction with the chosen value of magnetizing inductance, and the 60-kHz modulator frequency, delivers the required input power to meet the rated output load power, at minimum bulk voltage ripple.

This equation calculates a value of 207 mΩ. Use the nearest standard E24 value of 200 mΩ.

9.2.4.6 Transformer Constraint Verification

As outlined in Magnetic Sensing: Power Stage Design Constraints, there are constraints on the ratio of R_CS/L_PRI to ensure the design is consistent with the required volt-seconds for output sampling at minimum load, and with the controller t_ON(min) at high line. Per Equation 15 and Equation 16, limit the ratio of R_CS/L_PRI.

and,

In this case, the ratio equates to 769, so both constraints are met.

9.2.4.7 Transformer Selection and Design

After determining the value of current sense resistor R_CS, determine the maximum peak current at maximum demand point on the modulator. Accommodate for the I_PEAK adjustment for frequency dithering. Use this value when calculating the margin for core saturation. In this case, I_PK(sat) calculates to 4.13 A.

In subsequent calculations of required primary turns etc, the average maximum peak current, I_PK(max) , during the frequency dither period should be used, which calculates to 4.0 A.

Knowing I_PK(max), L_PRI and the turns ratio, the choice of transformer size and core shape and type dictates the required number of primary, secondary and bias turns, and the size of the air-gap. Various trade-offs, design preferences, and transformer design targets (size, cost, target losses, etc.) influence the specific choice of transformer core in any given design.

In the case of the UCC28630EVM-572 (PWR572 EVM), core area-product geometry was used to choose the minimum core size available to meet the power level. The core geometry factor K_g is a figure-of-merit that reflects the core power capability, in terms of its physical size, shape and design. It combines the core effective cross-sectional area, A_e, winding window area, A_w, and the mean length per turn (MLT) of wire around the core.

Estimate the required design core geometry, K_G(des), using the required transformer inductance L_PRI, maximum peak current I_PK(max), allowed maximum core flux density B_max and a target copper loss budget, P_CU.

K_u can often be as low as 25%, due to the fill factor (gaps between wires), wire insulation (especially for triple-insulated wire), and the need for insulating tapes and EMC shielding layers. The estimate of the required core geometry needs an estimate of the aggregate total winding current I_TOT. The analysis models the flyback transformer primary and secondary windings as a single lumped non-isolated inductor (such as a single winding buck inductor), only for the purpose of sizing the required core winding window to achieve the target copper loss. In this case, the secondary-side current amplitude reflects to the primary side so that aggregate total primary current. I_TOT can be estimated in Equation 33.

At rated power and minimum bulk capacitor voltage, the inductance L_PRI has been chosen to achieve boundary-mode conduction, therefore the duty cycle is given in Equation 34.

and

At the boundary conduction point, the primary peak current I_PK is at the level set by the modulator, V_CS(bcm). So from Equation 33, I_TOT becomes Equation 36.

Equation 36 calculates I_TOT as 2.6 A. Thus the required design K_G(des), assuming K_U of 25%, B_max of 315 mT and a target of 1-W copper loss, is shown in Equation 37.

Equation 37 indicates that this design requires a core size and shape with a K_G of more than 6.9 × 10^-12. A review of commonly used cores indicated that the RM10/I core set meets this requirement. With A_e of 96.6 mm², A_w of 44.2 mm² and mean length per turn (MLT) of 52 mm, K_G(RM10) is 7.9 × 10^–12, giving some margin over the design target.

With the chosen core, the actual primary, secondary-side and bias turns can be calculated. The required primary turns depend on the allowed B_max. For most power ferrites, a value in the region of 315 mT is commonly used.

Round N_P to 34. Now the required secondary-side turns can be calculated, using the previously calculated turns ratio per Equation 23.

Again, N_S is rounded to 6. Due to the integer rounding of the turns count, ensure that the actual turns ratio is within 5% of original target (if outside this range, secondary-side rectifier or primary MOSFET stress may be too high).

From Equation 24, the required bias turns can be calculated using Equation 42.

Again, N_B is rounded to 4. The effect of integer scaling in the turns is verified by calculating the expected bias voltage versus target.

The V_BIAS target was 12 V, so this is acceptable.

The required core inductance factor, A_L, to achieve the target inductance can be calculated as in Equation 44. The transformer manufacturer uses this factor to gap the core center leg.

Finally, calculate the required air-gap length l_g, based on the required inductance and the core geometry.

For the RM10/I core in 3C95 material (chosen for low core loss over a wide temperature range), the required air-gap length is calaulated using Equation 46.

Typically, the air-gap calculation in Equation 45 underestimates l_g, due to flux fringing in the air-gap. The fringing causes the affective area of the air-gap A_g to be somewhat larger than the ferrite core center leg A_CENTRE, depending on the gap length. This difference requires an increase in the required air-gap length to get the required inductance, which results in a further increase in fringing. However use Equation 45 to determine an initial value for l_g, which can then be used to estimate A_g. For round centre legs, the increase in effective area within the gap can be estimated empirically from Equation 47

(For more information about this subject, download the paper Inductor and Flyback Transformer Design, Lloyd Dixon, TI Power Supply Design Seminar SLUP127).

Because Equation 45 assumes that A_g equals A_CENTRE, it must be modified using Equation 48.

Re-iterating the air-gap calculation in Equation 49 .

Typically, after the second iteration above in Equation 48, the estimated air-gap is very close to the required value. Further iterations can be made, but should not be necessary.

9.2.4.8 Slope Compensation Verification

After choosing the current sense resistor, transformer inductance and transformer turns ratio, verify the required slope compensation against the fixed internal slope compensation. The worst case slope compensation requirement always occurs at the highest duty cycle operating point (at minimum bulk voltage level).

For stability, the slope compensation should be at least 50% of the difference between the inductor up-slope and down-slope. [reference Bob Mammano TI Power Supply Design Seminar paper, 2001, SLUP173]. For a flyback converter, the difference in slopes in CCM is equal the operating duty cycle multiplied by the inductor current down-slope value. For example, for 50% d_BULK(min) at minimum bulk capacitor voltage, the required slope compensation ramp is 25% of the inductor current down-slope.

As listed in Table 8, the specified peak-load transient is 130 W for 2 ms. In a worst case, peak transient timing with respect to the AC phase, the V_BULK minimum level dips to 65 V. This corresponds to a duty cycle of approximately 63.5% according to Equation 50.

The required slope compensation ramp is calculated at 63.5% duty cycle.

This value is within the 30 mV/μs of internal slope compensation provided by the controller.

9.2.4.9 Power MOSFET and Output Rectifier Selection

The initial design target proposed the use of a 100-V Schottky rectifier. The secondary-side reverse voltage stress can be verified using the final transformer design sh own in Equation 52.

The value derived from Equation 52 is close to the original design target of 85 V.

For 65-W load, the average DC output current is 3.35 A for 19.5-V output. However, to reduce losses, a much higher current rated diode is typically used, to yield a much lower forward voltage drop V_RECT. As shown in Figure 44, a 30-A rated diode D7 is used in this case, with a forward drop of approximately 0.45 V at 3.5 A, 100°C.

For the primary-side MOSFET, the peak voltage stress can be estimated using Equation 53.

An allowance of at least 100 V must be added to this figure to account for the leakage inductance spike at turn-off. This voltage spike depends on the transformer implementation and the amount of leakage inductance, as well as the specific design of the snubber. A more aggressive snubber may reduce the voltage spike, but at the expense of higher losses in the snubber. A voltage rating of at least 600 V is recommended for the power MOSFET to allow for leakage.

The MOSFET rms current at low line, rated load, can be estimated using Equation 54.

As can be seen in Figure 44, the chosen MOSFET Q1 is a 13-A, 600-V device.

9.2.4.10 Output Capacitor Selection

Select the output capacitor value on the basis of one of the following, depending on which one is the limiting factor:

• Required ripple current rating to absorb the high secondary-side peak current
• Required esr to achieve a target peak-peak ripple voltage
• Required holdup capacitance to achieve target minimum output voltage for a specified load transient from no load when the device is switching at f_SW(min)

For flyback converters, ripple current rating often dictates the output capacitance value. The required ripple current rating can be calculated from Equation 55.

At rated 65-W load, I_CAP(rms) = 5.9 A_RMS. Capacitors C11 and C13 in Figure 43 are chosen to meet this ripple requirement, (each capacitor has a 2.5-A minimum rating at 105°C). Total output capacitance is 1360 μF.

9.2.4.11 Calculation of CC Mode Limit Point

Calculate the expected output constant-current (CC) limit point from Equation 20. As previously noted, K_CC1 is 44.5 and K_CC1 is 69.5. Thus, I_OUT(lim) in this case is approximately calculated in Equation 56.

9.2.4.12 VDD Capacitor Selection

Size the VDD capacitor to supply sufficient I_DD(run) current to the device during initial start-up, and also during the charging phase of the main output capacitors. During the charging phase the bias winding on the transformer must supply the bias power. When VDD reaches the V_DD(start) threshold, the device consumes I_DD(run) for t_START(del) before the PWM switching commences. Thereafter, the bias current is the device current plus the MOSFET gate current. The VDD capacitor must support this higher level of current until the output is sufficiently charged that the bias winding rail has increased above the V_DD(stop) level.

Calculate the required bias capacitance from the total bias charge associated with the device run current during the t_START(del) phase, plus the device run current during the output charge phase, plus the primary MOSFET gate charge current during the output charge phase. The time taken for the output charge phase to reach a sufficient level to supply the bias can be calculated from the size of the output capacitor, target output regulation voltage, and the difference between the available CC mode current limit and the maximum load current (assuming that the output capacitor has to be charged whilst also supplying full rated load current). Assume that the MOSFET is switched at 60 kHz throughout the charging phase.

Combining these into one equation, the required VDD capacitor can be calculated as shown in Equation 57.

This can be re-written with the explicit device values substituted:

For this EVM design, the MOSFET Q_g(tot) is 30 nC, V_BIAS(nom) is 12.6 V. I_O(max) is 3.35 A, so this equates to:

Choose the next higher standard value, 22 μF.

Verify that the bias capacitance is sufficient to absorb all the X-capacitor energy when it has to be discharged, per Equation 3. From Figure 44, the value of X-capacitor is 330 nF.

9.2.4.13 Magnetic Sense Resistor Network Selection

The required values for the magnetic sense divider network are calculated from Equation 11 and Equation 12. For the RM10/I transformer used in the PWR572 EVM, the secondary-side to bias leakage inductance was measured and found to be approximately 4%. This figure can be reasonably estimated as the ratio of the inductance value measured across the secondary-side pins with the bias pins shorted together (primary winding should remain open-circuit), to the inductance value measured across the secondary-side pins with all other windings open:

R_A is calculated as shown in Equation 62.

The nearest standard E96 value 22.6 kΩ is selected. R_B may then be calculated to set V_OUT at 19.5 V.

The nearest E96 value is 32.4 kΩ, which could be used, but results in some set-point regulation error. As shown in Figure 44, the setpoint may be fine-tuned by using two parallel resistors for R_B. In this case use values of 39 kΩ and 180 kΩ, to give a net equivalent of 32.05 kΩ, very close to the target value in Equation 63.

Note that the pull-up diode to DRV pin should be a standard switching signal diode such as BAS21 or similar. The reverse recovery of the diode should be 100 ns or less. A slow-recovery diode clamps the VSENSE pin low for an initial portion of the flyback interval, and may impair or prevent the ability to take a valid output voltage sample.

9.2.4.14 Output LED Pre-Load Resistor Calculation

As shown in Figure 44, the output power good LED1 and series resistor R18 form an output pre-load or minimum load. This pre-load is necessary in order to maintain regulation at no load, or when the power converter output is disconnected from the load system. Magnetic regulation relies on sensing the output voltage during switching cycles, so it is necessary to maintain a certain minimum switching frequency f_SW(min) in order to continue sensing the output voltage. However, generating switching cycles at f_SW(min) transfers energy to the output, which requires some load on the secondary-side to absorb this energy and prevent the output capacitors from being charged out of regulation. The minimum energy transferred at f_SW(min) depends on the choice of magnetizing inductance L_PRI and current sense resistor R_CS.

In order to ensure that the control loop operates at a frequency above the minimum switching frequency, f_SW(min) (to ensure that the loop has adjustment range up/down as required to maintain regulation), the recommended minimum pre-load is at least twice the value calculated in Equation 64.

The required value of R18 can then be calculated, assuming a forward voltage drop of 1.8 V for the LED:

Use the next lower E24 value of 8.2 kΩ. For a design without an LED, a pre-load resistor of similar value is still required across the output voltage.

Table 9. Standby Power Performance

STANDBY POWER
115 VAC (mW)	230 VAC (mW)
57	60

Table 10. Average Efficiency Performance

AVERAGE EFFICIENCY (INCLUDING OUTPUT 76-mΩ CABLE DROP)
LOAD LEVEL (%)	115 VAC (%)	230 VAC (%)
25 (16.25 W)	89.44	89.26
50 (32.5 W)	88.98	89.38
75 (48.75 W)	88.24	89.10
100 (65 W)	87.59	88.73
Average	88.6	89.1