JAJSBZ0 データシート

JAJSBZ0D March 2014 – December 2017 UCC28630 , UCC28631 , UCC28632 , UCC28633 , UCC28634

PRODUCTION DATA.

11 Layout

11.1 Layout Guidelines

11.1.1 HV Pin

This pin is connected to the rectified AC input, and as such requires appropriate separation to other PCB traces to meet the application requirements for functional isolation;
This pin must have 200 kΩ of external resistance to allow the line voltage to be sensed for the X-capacitor discharge block. At least two series resistors should be used to reduce the voltage across the pins of each resistor, with each resistor rated for at least 200 V;
The connection to the resistors that feed the HV pin should have separate dedicated rectifying diodes from the AC input lines, to avoid the DC filtering that the bulk capacitor provides after the main diode bridge; the lower section of the main diode bridge can be shared by the device and the power stage;
A filtering or noise-decoupling capacitor is not recommended, such a capacitor will degrade the X-capacitor sampling ability to distinguish AC from DC input.

11.1.2 VDD Pin

A 1-µF ceramic decoupling capacitor is recommended, placed as close as possible between the VDD pin and GND, tracked directly to both pins.

11.1.3 VSENSE Pin

The tracking and layout of the VSENSE pin and connecting components is critical to minimizing noise pick-up and interference in the magnetic sensing block. (See Figure 63 for suggested component placement and tracking). Reduce the total surface area of traces on the VSENSE net to a minimum.
Because the resistance values of R_A and R_B are relatively high to minimize power dissipation, the high impedance makes the VSENSE pin potentially noise-sensitive. To minimize noise pick-up, locate resistors R_A and R_B as close as possible to the VSENSE pin, with R_B in particular placed as directly as possible between VSENSE and GND pins;
Depending on layout, a small noise filter capacitor may be useful on the VSENSE pin, such as C15 shown in Figure 44. Connect this capacitor as directly as possible between the VSENSE and GND pins. Choose the value of this capacitor as small as possible, and no greater than 10 pF. A larger value significantly delays the voltage rise-time at the pin, and affects the regulation set-point;
In case of possible board faults that can pull the VSENSE pin below GND (such as R7 shorted), in order to protect the pin and limit possible negative current out of the pin, a series resistor R4 (as shown in Figure 44) and clamping diode from GND are recommended. Maintain the value of R4 between 100 Ω and 500 Ω. A larger value may affect regulation and line sense accuracy.
For correct line sense operation, the switched pull-up R10 and D4 must be added. The value of R10 must be 3.9 kΩ to match the internal device gain. The switched pull-up diode and the GND clamping diode can be combined into a dual-diode common-cathode package, such as D4 as shown in Figure 44.

11.1.4 CS Pin

A small, external filter capacitor is recommended on the CS pin. Track the filter capacitor as directly as possible from the CS to GND pin.
Referring to Figure 44, a series resistor such as R5 is typically connected between the current sensing resistor R16 and the CS pin to form an R-C filter. A filter time constant between 100 ns and 200 ns is recommended. If the filter time constant is made too large, the filtering causes the transformer peak current to exceed the control loop demand level, which affects regulation and standby power. Place resistor R5 as close as possible to the CS pin.
Reduce the total surface area of traces on the CS net to a minimum.

11.1.5 SD Pin

Referring to Figure 44, the SD pin is connected to a temperature-sensing NTC RT1 in series with an adjust resistor R6. The NTC can be tracked to the required hot-spot location, or it can be wired with flying leads to the required hotspot.
Track the RT1 return to GND as directly as possible back to the GND pin of the device. RT1 should not be connected to a power GND track or plane, in order to minimize error in the trip level.
The device internally filters the SD pin, so an external filter capacitor is not usually required. If the application design requires an external capacitor, limit the value to 1 nF maximum.

11.1.6 DRV Pin

The DRV pin has high internal sink/source current capability. An external gate resistor is recommended. The value depends on the choice of power MOSFET, efficiency and EMI considerations.
As shown in Figure 44 an anti-parallel path formed by D5 and R13 are placed across the gate resistor R11 to allow turn-on and turn-off of the MOSFET to be independently adjusted.
A pull-down resistor (such as R15 in this example) on the gate of the external MOSFET is recommended to prevent the MOSFET gate from floating on if there is an open circuit error in the gate drive path. The value of R15 also affects the overload timer settings, so carefully choose the value of R15 according to Table 2.
Ensure that the noisy gate drive traces are routed away from the sensitive VSENSE pin and CS pin traces.

11.1.7 GND Pin

Connect decoupling and noise filter capacitors, as well as sensing resistors directly to the GND pin in a star-point fashion, ensuring that the current-carrying power tracks (such as the gate drive return) are track separately to avoid noise and ground-drops that could affect the analogue signal integrity.

11.2 Layout Example

UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 fig55_lusbw3.gif

Figure 63. Recommended PCB Layout for Single-Sided Assembly