To enable communication between a low-voltage MAC and a PHY of a different voltage level, a high-speed voltage translator with tight output channel-to-channel skew is recommended. To meet these system requirements, consider the SN74AXC8T245. To use the SN74AXC8T245 in this application, the six transmit signals, TXC, TXD [0…3], and TX_CTL should share one device. The six receiving signals, RXC, RXD [0…3] and RX_CTL use a separate SN74AXC8T245. It is recommended that the transmitter clock and data signals, as well as the receiver clock and data signals, are on the same device. A small difference in propagation delay between the output channels (skew) of the device could have a negative effect on the strict timing budget of the RGMII interface.

The bus-hold circuit avoids unknown voltage levels caused by floating inputs. Bus-hold circuitry allows the voltage translator to retain the last known output state in the event an input becomes high impedance or floating. This is useful in systems where peripherals may turn off intermittently or in cases where peripherals are plugged into a backplane via a plug-in card as in the case of Ethernet-PHY. See the System Considerations for Using Bus-hold Circuits to Avoid Floating Inputs application report. Devices with integrated bus-hold circuitry on the input and output ports, like the SN74AXCH8T245, are commonly used for many of the enterprise and communication applications.