SCEA065B November   2018  – March 2021 SN74AVC4T774 , SN74AXC1T45 , SN74AXC4T245 , SN74AXC4T774 , SN74AXC8T245 , SN74AXC8T245-Q1 , SN74AXCH1T45 , SN74AXCH4T245 , SN74AXCH8T245

 

  1.   Trademarks
  2. 1Introduction
  3. 2Common Interfaces and AXC Implementation
    1. 2.1 General Purpose Input Output (GPIO)
    2. 2.2 Serial Peripheral Interface (SPI)
      1. 2.2.1 Voltage Translation for SPI
      2. 2.2.2 SPI Applications
    3.     8
    4. 2.3 UART
      1. 2.3.1 Voltage Translation With UART
      2. 2.3.2 UART Applications
    5. 2.4 Joint Test Action Group (JTAG)
      1. 2.4.1 JTAG Applications
    6. 2.5 Reduced Gigabit Media Independent Interface (RGMII)
      1. 2.5.1 Voltage Translation for RGMII
      2. 2.5.2 RGMII Applications
      3. 2.5.3 Skew Performance
  4. 3Summary
  5. 4Related Documentation
  6. 5Revision History

1 Introduction

The AXC family of devices belong to TI's direction-controlled level translator family. These voltage translators use two separate configurable power supply rails to up- or down-translate incoming signals. The AXC translators are designed for an ultra-low VCC range of 0.65 V to 3.6 V, making them the lowest voltage level translator available in the industry. This allows the device to communicate with advanced processors operating at low-voltage nodes of 0.7 V, 0.8 V, or 0.9 V. The wide VCC range also accommodates the industry standard voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V) commonly found in processors and peripherals. These devices support data rates of up to 380 Mbps while providing 12 mA of drive strength. VCC isolation, IOFF functionality, and built-in ESD (electro static discharge) protection with 8-kV HBM (human body model) and 1-kV CDM (charged device model) are all features standard across this family of devices. Refer to Table 1-1 for information on the AXC family.

Table 1-1 AXC Family Features
PARAMETERAXC FAMILY
Voltage Support0.65 V–3.6 V
Data Rate380 Mbps
Drive Strength12 mA
Icc (AXC1T at 125°C)14 µA
ESD Ratings8-kV HBM, 1-kV CDM
Operating Temperature-40°C to 125°C
Power SequencingNot Required
Ioff Partial power downSupported

Most of the devices in the family have a version with bus-hold functionality, denoted by “H” as in AXCH*. Bus hold circuitry allows the voltage translator to retain the last known output state in the event an input becomes high impedance or floating. See the System Consideration for Using Bus-Hold Circuits to Avoid Floating Inputs application report for more information. The 4-bit and 8-bit devices feature two direction control pins allowing two independent banks of buses on a single device. This allows more control in how the device can be provisioned for simultaneous up- and down-translations; and, ideally reduces the BOM count. Additionally, these devices include an output enable pin to put all outputs in a high impedance state which also reduces power consumption. All devices in the family were designed to ensure glitch free power sequencing across hundreds of possible start up or shut down conditions. This allows either supply rail to be powered on or off in any order without causing a glitch at the output. See the Glitch Free Power Sequencing with AXC Level Translators application report.