SLLA383A February   2018  – August 2022 SN65HVDA100-Q1 , SN65HVDA195-Q1 , TLIN1022-Q1 , TLIN1029-Q1 , TLIN2022-Q1 , TLIN2029-Q1 , TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 LIN Specification Progression
    2. 1.2 Workflow Concept
  4. 2Network Architecture
    1. 2.1 General Layout of the LIN Bus
    2. 2.2 Serial Communication Principles
    3. 2.3 Commander-Responder Principle
    4. 2.4 Message Frame Format
  5. 3Physical Layer Requirements
    1. 3.1 Bus Signaling Fundamentals
    2. 3.2 Pullup Values
    3. 3.3 Threshold Values
    4. 3.4 Bit-Rate Tolerance and Timing Requirements
    5. 3.5 Synchronization and Bit Sampling
    6. 3.6 Duty Cycle
  6. 4Filtering, Distance Limitations, Nodes on Bus
    1. 4.1 EMI and Signal Conditioning
    2. 4.2 ESD and Transients
    3. 4.3 Distance and Node Limitations
  7. 5LIN Transceiver Special Functions
    1. 5.1 Low-Power Modes
      1. 5.1.1 Sleep Mode
      2. 5.1.2 Standby Mode
    2. 5.2 Wakeup
      1. 5.2.1 Pin Wakeup
      2. 5.2.2 LIN Wakeup
      3. 5.2.3 Dominant Timeout
  8. 6Advantages and Disadvantages
  9. 7Conclusion
  10. 8Revision History

3.5 Synchronization and Bit Sampling

Barring a special use case, all bit times use the bit timing of the commander node as the reference. The synch byte consists of ‘0x55’ (8 bits of alternating 1’s and 0’s, starting with 0) which is essentially a clock signal at a given frequency. The falling edges of the pattern are used for synchronizations that are combined with the start and stop bit (10 bits total), which allows 4 total falling edges for synchronization of the responder nodes. This also allows for accurate bit width (TBIT) measurement. However, because of different methods of synchronization on the market being used in terms of bit sampling (not necessarily on the falling edge of the start bit), the LIN 2.2 specification removed the specification of start-bit sampling. This allows all methods for start-bit sampling that meet the timing requirements of the byte field synchronization (tBFS, which is defined as 1/16 of TBIT typical, 2/16 TBIT maximum).

GUID-D44854DC-9AE8-497C-940A-0378C124530B-low.gifFigure 3-4 Bit Sampling Illustrated

After synchronization of the responder nodes occurs, each bit must be sampled accurately to ensure proper interpretation of the message by the LIN cluster. Each bit shall be sampled between the earliest bit sample (tEBS) and the latest bit sample (tLBS); tLBS is dependent on tBFS via Equation 1:

Equation 1. tLBS = 10/16 TBIT – tBFS

TEBS is defined as minimum 7/16 TBIT. The rest of the bits after the first bit are then sampled with a sample rate (tSR). These are based on the earliest bit sample of the former bit (n – 1) and the earliest bit sample of the current bit (n), and given by the following equation:

Equation 2. tSR = tEBS(n) – tEBS(n – 1) = TBIT