6 Summary

Some high voltage, high frequency applications scenarios do expose the gate driver to short input pulses and it is important for system designer to understand the impact of non-zero current switching from applying narrow pulses that can lead to internal stresses of the gate drive which can lead to damage of components inside the gate driver. To make sure safe operation, a complete transition is achieved when the V_GS = VDD is met and no I_G current flows to charge the external load. For the turn-ON condition, the recommendation is to have the driver output rise to higher than 90% of VDD before changing states again to achieve a Zero Current Switching. In the case of a turn-off pulse, have the output fall to less than 10% of VDD before turning back on. This will make sure that large voltage spikes are not generated due to non-zero current switching of a high current in the presence of inductive parasitic on the PCB and in component package connections. In addition, sizing R_G to help limit the di/dt for the gate driver, providing enough margin between VDD abs max and the operating condition, and proper decoupling capacitor placements can help mitigate issues in the driver from narrow pulses.