SLVAF66 June 2021 DRV3255-Q1 , DRV8300 , DRV8301 , DRV8302 , DRV8303 , DRV8304 , DRV8305 , DRV8305-Q1 , DRV8306 , DRV8307 , DRV8308 , DRV8320 , DRV8320R , DRV8323 , DRV8323R , DRV8340-Q1 , DRV8343-Q1 , DRV8350 , DRV8350F , DRV8350R , DRV8353 , DRV8353F , DRV8353R
Unfortunately, there are adverse effects of a high slew rate in a high-power system. The inherent capacitive coupling of the MOSFET, and the effects of parasitic LC resonance increase as more current flows through the FETs and the VDS voltage transitions more quickly.
As shown in Figure 3-1, the high-frequency component of the rising edge of the gate signal—and more importantly, the rising VDS signal going through the Miller region—causes current to flow onto the intrinsic capacitors of the other FET. This signal couples through the inherent gate-to-drain or gate-to-source capacitor because capacitors have lower impedance at higher frequencies. If these coupled signals are high enough, they can exceed absolute maximum ratings of the motor driver or turn on the low- and high-side FETs within one phase to cause a shoot-through condition as current bypasses the motor and flows through the direct path from VDRAIN to GND.
MOSFETs have a limit of maximum slew rate before they turn on due to CGD coupling. This means that if the slew rate is too high—even if the gate is shorted directly to the source—the MOSFET turns on. When considering the gate driver pulldown strength and parasitic inductance on the gate path, this reduces the maximum slew rate possible before causing unintentional turn-on.
Simply put, higher gate current means more coupling, and less gate current means less coupling.
To reiterate:
Now that the effects of too much gate current are understood, methods to adjust the gate current must be developed and calculation of a gate current for a given system must be derived.