SLVAF66 June 2021 DRV3255-Q1 , DRV8300 , DRV8301 , DRV8302 , DRV8303 , DRV8304 , DRV8305 , DRV8305-Q1 , DRV8306 , DRV8307 , DRV8308 , DRV8320 , DRV8320R , DRV8323 , DRV8323R , DRV8340-Q1 , DRV8343-Q1 , DRV8350 , DRV8350F , DRV8350R , DRV8353 , DRV8353F , DRV8353R
For this example, the DRV835x family of devices is used and paired with the CSD19536KTT power MOSFETs, which are used in the 54-V, 1.5-kW, > 99% efficient, 70 × 69 mm2 power stage reference design for 3-phase BLDC motors: TIDA-010056.
The steps for estimating the approximate gate current generally are:
Where:
For the case of the CSD19536KTT, Qgd = 17 nC and we can use the general guidelines to put 100 ns into the rise and fall time of Equation 3. Note, some designers like to make the fall time two times faster than the rise time.
The DRV835x family does not have an IDRIVE setting of exactly 170 mA, but it does have lower options of 150 mA or 100 mA for source current and 100 mA for sink current. Source refers to the current taken from the gate voltage supply and pushed into the FET, which corresponds with the rise time; and sink refers to the rate at which charge is pulled from the gate of the FET and pushed to the source of the FET, which corresponds with the fall time.
In the case where the rise and fall time is 300 ns, the same equation can be used:
Using the DRV835x family again, choose 50 mA for the source current but the smallest sink current is 100 mA. This is a perfect example for replacing the 0-Ω gate resistor with a nonzero value to get the equivalent gate sink current below the lowest setting. If not planning to have the 0-Ω gate resistor, traces must be cut and the board redesigned to get the desired performance.
Remember, we are merely using a starting gate drive current that was calculated with a safe general guideline. This is a first order equation and does not exactly match what is seen in the real system, but the goal is to get within a reasonable starting point. This is why we round down if the device does not have an exact selection, to make the equivalent rise or fall time to be longer than the calculated value. Designers are expected to increase or decrease this number after testing.