The first step in the troubleshooting process is to understand where the damage occurred. Check the functions of the power stage to evaluate if any function no longer works as intended after damage has occurred.

For the case of delivering current to the motor, take a Digital Multimeter (DMM) and perform an impedance check between drain and source of the FETs, or VDRAIN and SHx shown in Figure 2-1. The drain-to-source path is expected to be high impedance (that is, kΩ) when unpowered so low impedance indicates damage to the FETs and current delivery path. For more troublesome troubleshooting, use an oscilloscope to probe the gate voltage, drain voltage, and source voltage at the FET during a transition to check for stability and the amount of ringing on the signals.

In the case of voltage translation, take a DMM and perform an impedance check between the gate signals and the gate voltage supplies, such as VGLS, VCP, or GND as shown in Figure 2-1. These paths are expected to be high impedance with a capacitive load. Low impedance signifies damage (that is, ones of ohms). For more in-depth troubleshooting, use an oscilloscope voltage probe to check the stability of the voltage supplies during operation.

For the case of conditioning or protecting gate signals, take a DMM or LRC meter and do an impedance check on the components in the path to ensure the passive components were not damaged. Simply comparing the read value with the expected value listed in the schematic is an easy way to check for damage.

It is important to note that most motor drivers integrate these functions into one device or piece of silicon. As a result, most of these integrated gate drivers are able to monitor and check these functions and notify the designer with some sort of FAULT, WARNING, LOCK GPIO signal, or read-able register. If the nFAULT signal is asserted, it is critical to understand why the nFAULT signal is asserted and which fault is triggered. Criteria for every fault is usually provided in the data sheet. More importantly, if the nFAULT signal can be reset, the signal can be monitored with an oscilloscope voltage probe and used as a falling-edge trigger to capture other signals, such as the FET gate, source, or drain voltages.

In summary, the steps are:

• Use a DMM to check impedance between all terminals of the FETs
• Use an oscilloscope to probe gate, drain, and source voltages to check for stability and ringing
• Use a DMM to check impedance between the gate and gate voltage supplies
• Use an oscilloscope to probe gate supply voltages for stability
• Use a DMM or LCR to confirm passive component values in power stage
• Understand the cause for any FAULT signals asserted

Fortunately, high-power design does not primarily need to be an experiment that takes place after something has gone wrong. As previously mentioned, there are actions that can be taken to mitigate potential problems.

These actions may result in a different board architecture or different operation of gate driver leading to more components or board area. As such, there are tradeoffs between implementing every possible action, and considering the most important requirements of the real system - this is the art of high-power design.