SNLA475 October 2024 DS250DF410 , DS250DF810 , DS280BR810 , DS280BR820 , DS280DF810 , DS280MB810 , DS560MB410
DS280MB810 includes mux select inputs on pins E2 (MUXSEL0) and E14 (MUXSEL1). MUXSEL0 controls the crosspoint for channels 0–1 and 4–5, and MUXSEL1 controls the crosspoint for channels 2–3 and 6–7. The crosspoint can also be controlled entirely via SMBus register writes.
There are 2 options regarding mux select input connections to DS280MB810 within this codesign example.
DS2x0DF810 and DS280BR8x0 do not include mux select inputs. The crosspoint on DS2x0DF810 is controlled entirely via SMBus register writes. DS280BR8x0 does not include any crosspoint capability. On DS2x0DF810 and DS280BR8x0, pins E2 (TEST0) and E14 (TEST1) are reserved TI test pins which can be left floating, tied to GND, or connected to a 2.5V output. This codesign example includes 1kΩ pull-downs to GND when R11 and R12 are populated and R6 and R7 are depopulated.