SPRACN9F May   2023  – August 2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1

 

  1.   1
  2.   Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 Design Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Supporting Documentation
    2. 1.2 Board Designs Supported
    3. 1.3 General Board Layout Guidelines
    4. 1.4 PCB Stack-Up
    5. 1.5 Bypass Capacitors
      1. 1.5.1 Bulk Bypass Capacitors
      2. 1.5.2 High-Speed Bypass Capacitors
    6. 1.6 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK, CMD_ADDR, and CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK, CMD_ADDR, and CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 Simulation Integrity Analysis
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Waveform Quality
        2. 3.5.3.2 Eye Quality
        3. 3.5.3.3 Delay Report
        4. 3.5.3.4 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Revision History

2.14 Data Group Routing Specification

Skew within the Byte signal net class directly reduces the setup and hold margin for the DQ and DM nets. As described with the ADDR_CTRL signal net class and associated CK clock net class, this skew must be controlled. The data byte skew must be managed through controlling the lengths of the routed tracks within a defined group of signals. The only way to practically match skews on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. Make sure to include the Z-axis delays (vias) during analysis.

Note: It is not required nor recommended to match the lengths across all byte lanes. Length matching is only required within each byte.

Table 2-7 contains the routing specifications for the Byte0, Byte1, Byte2, and Byte3 routing groups. Each signal net class and its associated clock net class is routed and matched independently. These parameters are recommendations only, intended to get the design close to success prior to simulation. To ensure the PCB design meets all requirements, it is required the design be simulated and those results compared with the simulation results defined in Section 3.

Table 2-7 Data Group Routing Specifications
Number Parameter MIN TYP MAX UNIT
LP4_DRS1 Propagation delay of net class DQSx
RSD1 (4)		 300 (2) ps
LP4_DRS2 Propagation delay of net class BYTEx
RSD2		 300 (2) ps
LP4_DRS3 Propagation delay of each DQS pair must be less than propagation delay of CK pair. RSD1 < (RSAC1 + RSAC2) (4) 0 ps
LP4_DRS4 Skew within net class DQSx
RSD1 Skew (DQS+ to DQS-) (4)(5)		 0.75 ps
LP4_DRS5 Skew across net class DQSx and BYTEx
RSD1 to RSD2 Skew (1), (4), (5)		 5

25

 ps
LP4_DRS6 Propagation delay of each DQS pair must be less than propagation delay DQ/DM. RSD1 < RSD2 (4) 0 150 ps ps
LP4_DRS7 Vias Per Trace 2 (2) vias
LP4_DRS8 Via Stub Length (3) 40 Mils
LP4_DRS9 Via Count Difference 0 (6) vias
LP4_DRS10 RSD1 center-to-center spacing (between clock net class) (7) 4w
LP4_DRS11 RSD1 center-to-center spacing (within clock net class) (8), (9)
LP4_DRS12 RSD2 center-to-center spacing (between signal net class) (7) 4w
LP4_DRS13 RSD2 center-to-center spacing (within signal net class)(7) 3w
(1) Skew matching is only done within a byte. Skew matching across bytes is neither required nor recommended.
(2) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(3) Via stub length control (micro-via or backdrill) may be required if operating LPDDR4 above 3200 Mbps (depending on simulation).
(4) Consider the delays from SoC die pad to the DRAM pin (ie. Delays include SoC package plus PCB). Consider only one leg of any T-branch trace segments.
(5) To be verified by design/simulation, confirming JEDEC defined Vix_DQS_ratio (20%) are satisfied with good eye margins.
(6) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure DQn skew and DQSn to DQn skew maximums are not exceeded.
(7) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints). Spacing minimums may be relaxed if simulations accurately capture crosstalk between neighboring victim and aggressor traces show good margin. Also consider via spacing. Signals with adjacent vias near SoC should NOT have adjacent vias near DRAM.
(8) DQS pair spacing is set to ensure proper differential impedance.
(9) The Simulation Results must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer.