SPRACP4A December 2019 – June 2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1
The CSI-2 schematics vary, depending on the number of lanes implemented. Depending upon device, each CSI-2 can include up to four data lanes. General connectivity is straightforward and consistent between implementations. Figure 3-8 illustrates a CSI-2 system using a single lane.
The DSI schematics vary, depending on the number of lanes implemented. Depending upon device, each DSI can include up to four data lanes. General connectivity is straightforward and consistent between implementations. Figure 3-9 illustrates a DSI system using a single lane.