3 PFC CRM/ZVS Realization Based on Type-4 PWM

Figure 3-1 shows the signal interface from external PFC power stage hardware to C2000 internal peripherals to generate PWM signal. This report takes CMPSS5, X-BAR(TRIP5), ePWM1 as an example to explain the realization of CRM/ZVS PFC by type-4 PWM.

The input signal in Figure 3-1 is the PFC inductor current iL. This is chosen as an input to COMPH positive pin of the CMPSS module as detailed in Figure 3-2. The threshold for capturing current zero crossing (ZC) is a fixed value close to zero and applied to DACHVALS (shadow register DAC value). The current ZC threshold is set as the negative input of COMPH through the reference DAC. The invert output of comparator is chosen as CTRIPH and connected to X-BAR asynchronously.

The CMPSS5 CTRIPH signal connects to X-BAR TRIP5 mux8 as shown in Figure 3-3. In order to pass any signal through to the ePWM, enable the mux8 in the TRIP5MUXENABLE register. CMPSS output is fed into ePWM DC sub-module through ePWM X-BAR. TRIP5, refers to the inductor current negative zero crossing (NZC) event, generates DCAH signals by setting DCAHTRIPSEL.Note that positive zero crossing event is filtered by blanking window as shown in the Figure 3-7. Then, the configuration of TZDCSEL register qualifies the actions on the selected DCAH signal, which generates the DCAEVT1 event. The DCAEVT1 event then is filtered to provide DCAEVT1.sync with a filtered version of the event signals by configuring DCACTL. Then DCAEVT1.sync generates a synchronization pulse to the time-base counter.

Detailed event filtering logic block as shown in Figure 3-4 is critical to realize ZVS/ZCS. The event filtering block can capture the TBCTR value of the trip event to provide control algorithm with PWM period and store the period value in DCCAP register. The blanking logic is used to filter out potential noise and inductor current positive zero crossing (PZC) event on the signal prior to generating right sync signal. Figure 3-4 shows signal flow in the event filtering logic module. Select the DCAEVT1 events as an input to the event filtering logic block (DCFCTL[SRCSEL]) with a blanking window (Blank Control Logic). This is where the comparator output is selected as an input to the event filtering logic block. Blanking window is ANDed with DCAEVT1. Software trigger source is selected as an event to reset and restart the edge filter (VCAPCTL[TRIGSEL]). At the end, configure VCAPCTL[EDGEFILTDLYSEL] to apply delay (a software programmed value in SWVDELVAL) based on the hardware parameters. Now the DCCAP can capture the TBCTR value of the event associated with the inductor current negative zero crossing. This TBCTR value represents the period of the present PWM switching cycle.

At the end, DCAEVT1.sync is enabled by set DCACTL[EVT1SYNCE] of event triggering block as shown in Figure 3-5 and phase shift is enabled by setting TBCTL[PHSEN] of time base sub-module to sync TBCTR as shown in Figure 3-6.

Figure 3-7 shows the key signal waveforms after the peripheral configuration. The rising and falling edge of DCAEVT1 signal represents positive and negative zero crossing point accordingly based on Figure 3-7. Blanking window is ANDed with DCAEVT1 to generate DCEVTFILT so that inductor current positive zero crossing (PZC) edge and noise during the MOSFET on-time are filtered. In this way, the blanking window length should be longer than PWM on-time. DC sub-module applies a delay corresponding to inductor negative zero crossing (NZC) edge to generate sync event.