SPRADG5 January   2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1UART Introduction
    1. 1.1 Jacinto 7 UART Overview
    2. 1.2 Jacinto 7 UART Features
    3. 1.3 Jacinto 7 UART Functional Introduction
  5. 2UART Usage Overview
    1. 2.1 WKUP_UART0 Usage
    2. 2.2 MCU_UART0 Usage
    3. 2.3 MAIN_UARTx Usage
  6. 3Log Level Design on Software Module
  7. 4Change UART Instance
    1. 4.1 Change MAIN_UARTx for MAIN Domain
    2. 4.2 Set Standalone UART Port for DSP/MCU
  8. 5Summary
  9. 6References

1.1 Jacinto 7 UART Overview

Jacinto 7 series processors all have the same UART IP, so the functions and usage methods of UART on different processors in this series are basically the same. Table 1-1 shows that each processor has totally 11 UART interfaces, one of which is in the WKUP domain, one is in the MCU domain, and the remaining nine are in the MAIN domain. After all the domains are powered on normally, each core can access any of these UART through software. However, in the system software architecture, multiple cores should not access a UART at the same time. This may lead to some system conflicts, causing a certain core to hang.

Table 1-1 UART Allocation Across Device Domains
Instance Domain
WKUP MCU MAIN
WKUP_UART0 √ - -
MCU_UART0 - √ -
UART0 - - √
UART1 - - √
UART2 - - √
UART3 - - √
UART4 - - √
UART5 - - √
UART6 - - √
UART7 - - √
UART8 - - √
UART9 - - √