SPRADG5 January   2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1UART Introduction
    1. 1.1 Jacinto 7 UART Overview
    2. 1.2 Jacinto 7 UART Features
    3. 1.3 Jacinto 7 UART Functional Introduction
  5. 2UART Usage Overview
    1. 2.1 WKUP_UART0 Usage
    2. 2.2 MCU_UART0 Usage
    3. 2.3 MAIN_UARTx Usage
  6. 3Log Level Design on Software Module
  7. 4Change UART Instance
    1. 4.1 Change MAIN_UARTx for MAIN Domain
    2. 4.2 Set Standalone UART Port for DSP/MCU
  8. 5Summary
  9. 6References

Abstract

TI latest automotive processor Jacinto 7 series covers the automotive applications in ADAS and Gateway under different scenarios. It contains both TDA4X and DRA82X series which are mainly used for ADAS and Gateway respectively. These processors are based on multi-core heterogeneous architecture, consisting of Cortex®-R5, Cortex-A72, Cortex-M3/M4, DSP and some common peripherals. There is a high reusability within these processors. Normally, this series processors need to run an operating system and the related application threads on each core, involving the internal data transmission and peripheral calls. Hence, there is a pretty high complexity for the applications of Jacinto™ 7 series processors. Sometimes when a problem occurs, it is not that easy to debug.

This application note demonstrates the basic information on the hardware and software levels of the universal asynchronous receiver/transmitter (UART) logging system in the reference design provided by TI. It includes the way to customize customers’ own log output serial port based on the default SDK and reference design, and the method of debugging multi-core heterogeneous system-on-chips (SoCs) by printing the UART logs to solve the problems.