Abstract

This publication describes recommended power designs to support the J722S/AM67x/TDA4VEN/TDA4AEN family of processors as used on J722SXH01EVM - TDA4VEN, TDA4AEN and AM67 evaluation module. A selection guide that reviews system tradeoffs and design benefits is included to assist in power design selection, optimization and feature set comparisons. Power resource and control signal mapping block diagrams are provided to accelerate an end product’s design process.

Introduction

The J722S/AM67x/TDA4VEN/TDA4AEN processor line provides highly flexible, real-time, and low-latency processing for a broad range of automotive and industrial applications. The J722S/AM67x/TDA4VEN/TDA4AEN vision and display processor includes scalable Arm® Cortex®-A53 performance, image signal processor (ISP) up to 600MP/s, Deep Learning AI Accelerators up to 4 tera-operations-per-second (TOPS), Depth and Motion Processing Accelerators (DMPAC), Vision Processing Accelerators (VPAC), along with embedded features such as triple high-definition display support, high-performance 3D-GPU, 4K video acceleration, and many additional peripheral interfaces.

All Power Distribution Network (PDN) schemes described leverage TI Power Management ICs (PMIC) with a mixture of discrete power components to support a J722S/AM67x/TDA4VEN/TDA4AEN system. All power components are automotive AEC-Q100 qualified. The PDNs have been designed primarily to support all essential processing components, known as the SoC platform, which includes:

• J722S/AM67x/TDA4VEN/TDA4AEN SoC processor
• LPDDR4 SDRAM
• OSI or Octal NAND boot Flash
• eMMC mass storage Flash
• PDN power devices

The functional safety compliant TPS6522x12-Q1 PMIC and TPS6287x-Q1 fast transient, high current power stage (HCPS) form the PDN’s base power devices for the J722S/AM67x/TDA4VEN/TDA4AEN platform. Different PDN schemes can be used to support the SoC platform according to a system's maximum use case and desired features. A selection guide has been created that highlights the value and flexibility of PMIC centric PDN designs that leverages one common PMIC PN along with discrete power devices as needed to add optional features.

PDN Selection Guide

Selecting a J722S/AM67x/TDA4VEN/TDA4AEN power design begins with answering a few end product questions:

1. What is the desired processor performance?
2. What is the desired level of core voltage flexibility?
3. What is the desired PDN input voltage?
4. What are the desired optional features?
   1. Low-power modes: (Partial IO Retention only, Partial IO and DDR Retention)
   2. Key functions: (PMIC die temp monitoring, HS SoC eFuse programming, UHS-1 SD card)
   3. Target functional safety level: (None or ASIL-B)

Once a system's desired features are determined, then the tables below can be used to optimize a recommended power design that provides:

1. SoC processing peak power demands
2. SoC platform (SoC, LPDDR4, Flash, base power devices) voltages and control signals
3. Flexibility to make design trade-offs: PDN features versus PCB area and BOM cost

Key attributes that define a PDN are: base power devices, processing performance, input voltage, and optional features. For easy reference, a 2-part PDN identification code (for example, PDN-123.456x) defines a PDN’s attributes.

The 1st group of characters (-123) is known as the “ID” field and defines base power devices, processing performance and input voltage as follows:

1. Numeric value for base power devices:
   1. 5 = TPS62870/1/2/3-Q1 (HCPS) + TPS65223/112-Q1 (PMIC)
   2. 7 = TPS62874/5/6/7-Q1 (HCPS) + TPS65223/112-Q1 (PMIC)
2. Alphabetic letter for processing performance and resource mapping:
   1. A – D = 1.4GHz clock with 0.85V Core boot voltage
   2. L – P = 1.25GHz clock with 0.75V Core boot voltage
3. Numeric value for PDN input voltage:
   1. “None” = 3.3V default
   2. 5 = 5V

The 2nd group of characters (.456x) is known as the “Variant” field and defines optional features requiring add-on discrete power devices as follows:

D = Partial IO and DDR Retention low power mode (LPM)

E = On-board Efuse programming for high-security SoCs in-the-field

S = UHS-I SD card memory

J722S/AM67x/TDA4VEN/TDA4AEN EVM system (J722SXH01EVM - TDA4VEN, TDA4AEN and AM67 evaluation module) uses the PDN-7D.DES scheme to demonstrate flexible processor performance with all optional features.

Processor Performance

The J722S/AM67x/TDA4VEN/TDA4AEN processor can provide 2 basic levels of performance as dictated by the primary clock rate of 1.25 or 1.4GHz which requires 2 different VDD_CORE supply voltage levels of 0.75V or 0.85V, Table 1. A flexible processing PDN scheme has been defined as well that allows the processor to boot up at one performance level (1.4GHz, 0.85V or 1.25GHz, 0.75V) and then transition to a different performance level using system software. The flexibility to operate the processor at a lower clock and VDD_CORE voltage requires the 0.85V fixed input supplies (VDDR_CORE, VDD_MMC0 and VDDA_0P85_xxx) to be independently sourced, see VDD_RAM_0V85 power rail in Table 1. Optional processor low power modes (LPM) can be supported if an independent supply for VDD_CANUART is used to allow all other low voltage supplies to be disabled for SoC power reduction, see VDD_IORET_0V75 power rail in Table 1.

The J722S/AM67x/TDA4VEN/TDA4AEN processor has 3 key use cases across automotive and industrial markets, Table 2. Robust PDN designs must be able to support these processor use case operations under peak power conditions when the highest silicon junction temperature causes maximum leakage current and extreme processor resource usage causes peak dynamic currents.

The J722S/AM67x/TDA4VEN/TDA4AEN power estimation tool (PET) can be used to estimate a processor's power dissipation for different resource loadings per use case. The PET can provide both a PDN and Thermal power estimate. A PDN estimate gives the peak SoC loads over very short elapsed times (1-10us) during high processor resource demand conditions. The PDN or peak estimate is used for PDN design to ensure sufficient output current is available to support peak loads across all input supplies. A Thermal estimate gives the average sustained power over several minutes during maximum use case conditions. The Thermal or average power estimate is used for designing a processor’s thermal management system to avoid exceeding the silicon junction temperature (T_J) maximum.

Platform Support

PDN designs must support J722S/AM67x/TDA4VEN/TDA4AEN processor, SDRAM, boot and storage Flash memories, see Table 3. The base power devices are a functional safety-compliant PMIC (TPS6522312-Q1) and a high-current power stage (HCPS) using functional safety capable, fast transient, stackable buck converter (TPS62875B-Q1) to supply the heaviest processor load drawn by VDD_CORE supply.

PMIC TPS6522x12-Q1

The common TPS6522x12-Q1 PMIC can use 1 of 2 variant PNs: 1) TPS6522312X-Q1 that has an internal ADC to monitor either the PMIC T_J or on-board net voltage connected to a dedicated PMIC GPIO input by I2C. 2) TPS6522112-Q1 that does not have an ADC. The PMIC internal NVM settings (identified by the PN characters “12”) and pre-configurable finite state machine (PFSM) use four Resource Selection (RS) control signals to direct PMIC power and GPIO resource assignments as needed for implementing different PDN schemes. The optimized TPS6522x12-Q1 PMIC simplifies the design process, supports multiple PDN schemes, enables recommended power designs and reduces time to market. Table 9 provides an overview of the PMIC's basic features.

The PMIC Resource Selection (RS[3:0]) signals direct the PMIC power and GPIO resource assignments to support different PDN variants along with add-on discrete power resources as needed for optional features. All four RS control signals are captured during each PMIC cold boot power up sequence. The RS3 and RS2 bits are set automatically when the PMIC’s Pre-configurable Finite State Machine (PFSM) executes two sequences that leverage internal voltage comparators connected to VCCA and VMON1 inputs to determine the PDN input voltage and VDD_CORE supply levels respectfully. RS1 and RS0 bits are latched logic levels on PMIC's GPIO1 and GPIO2 inputs. The logic levels are set based upon the output voltage of a resistor divider network formed by the combination of PMIC weak, internal pull-up resistors (Rpu about 400k) to VIO supply and any on-board, pull-down resistors (Rpd = 10k) to ground. Table 10 summarizes the PMIC RS[3:0] operations and assignments.

In addition, TPS6522x12-Q1 PMIC supports a HW option to disable watchdog timer before a system cold boot which is useful during product development and debugging. The PMIC latches the logic level on GPIO6 pin during the execution of an SoC power up sequence. 


The logic level dedicates watchdog timer operation as follows:

a) High level disables the Watch-Dog Timer by setting WD_PWRHOLD bit to disable timer’s long-window time-out.

b) Low level enables Watch-Dog Timer by setting WD_PWRHOLD bit to enable timer’s long-window time-out.

After the PMIC's VCCA input supply is energized and completes NVM initialization, the GPIO6 pin is configured as an input with a weak pull-down resistance and set to nERR_MCU function to monitor SoC processing errors. The J722SXH01EVM - TDA4VEN, TDA4AEN and AM67 evaluation module schematic demonstrates how to connect the SoC's ERRORn output signal through a tri-stateable buffer to isolate the SoC's output from the GPIO6 input pin during the early portion of a power up sequence. This allows the GPIO6 input to be pulled up to PMIC's VCCA supply (either 3.3 or 5V) to disable the watchdog timer or the PMIC's internal, weak pull-down resistor sets a low logic level to enable the watchdog timer. The tri-stateable buffer is required to avoid current bleeding into an unenergized SoC output pin whenever disabling watchdog timer is desired at system cold boot. The latching of GPIO6 level occurs before the PMIC enables the VDD_IO_1V8 supply at 2.5ms time step. Once VDD_IO_1V8 is energized, the tri-state buffer is enabled to connect the SoC's ERRORn output signal to GPIO6 as desired for active system operation.

HCPS TPS6287x-Q1

The HCPS uses a high current, fast transit discrete buck converter TPS6287x-Q1 PN series capable of supplying output currents ranging from 6 to 30A in a single phase configuration. Two similar buck converters families are available with excellent fast transient performance, stack-able for multi-phase operation, different output current ranges, power optimized package types and similar register maps. An end product’s peak load during very demanding high processor resource use determines which buck PN should be used, Table 11. The buck PN selected and whether to use a multi-phase configuration is dependent upon the total output current capacity needed to provide a positive current margin vs peak load. A good power design practice is to design for +15% current margin for each power rail to enable potential processor resource increases or use case feature growth during development.

Table 12 shows PMIC and HCPS output voltages with start-up enabling and shut-down disabling sequence delays per TPS6522x12X-Q1 NVM elapsed time step settings. For more information on PMIC registers and NVM settings, see TPS6522x12X-Q1 user’s guide.

J722S PDN-7A with 3.3V input

PDN-7A uses 3.3V input voltage with only the base power devices to enable 1.4GHz processing for J722S/AM67x/TDA4VEN/TDA4AEN platform that supports in-field Efuse programming optional feature, Table 13.

Figure 1 1.4GHz, 3.3Vin, PDN-7A with Optional eFuse Programming

References

Automotive Components

• Texas Instruments, TDA4AEN-Q1, TDA4VEN-Q1 Jacinto™ Processors data sheet
• Texas Instruments, TPS65224-Q1 Power Management IC (PMIC) with 4 BUCKs and 3 LDOs for Safety-Relevant Automotive Applications data sheet
• Texas Instruments, TPS6287x-Q1, 2.7-V to 6-V Input, 6-A, 9-A, 12-A, 15-A, Stackable, Synchronous Step-Down Converters with Fast Transient Response data sheet
• Texas Instruments, TPS6287x-Q1, 2.7-V to 6-V Input, 15-A, 20-A, 25-A,and 30-A AutomotiveFast Transient Synchronous Step-Down Converter with I2C Interface data sheet
• Texas Instruments, TPS22965x-Q1 5.5-V, 4-A, 16-mΩ On-Resistance Automotive Load Switch data sheet
• Texas Instruments, TLV733P-Q1 Capacitor-Free, 300-mA, Low Dropout (LDO) Linear Regulator data sheet
• Texas Instruments, TLV7103318-Q1 Dual, 200mA, Low-I_Q, Low-Dropout Regulator for Portable Devices datasheet
• Texas Instruments, TPS7A21-Q1 Automotive, 500mA, Low-Noise, Low-IQ , High-PSRR LDO data sheet
• Texas Instruments, TPS61240-Q1 3.5-MHz High Efficiency Step-Up Converter data sheet

Industrial Components

• Texas Instruments, AM67x Processors data sheet
• Texas Instruments, TPS6287x, 2.7 to 6V Input, 6-A, 9-A, 12-A, 15-A, Stackable, Synchronous Step-Down Converters with Fast Transient Response data sheet
• Texas Instruments, TPS22965 5.7-V, 6-A, 16-mΩ On-Resistance Load Switch data sheet
• Texas Instruments, TLV7103318 Dual, 200mA, Low-Iq, Low-Dropout Regulator for Portable Devices data sheet
• Texas Instruments, TLV733P Capacitor-Free, 300-mA, Low-Dropout Regulator
• Texas Instruments, TPS7A21 500mA, Low-Noise, Low-IQ, High-PSRR LDO data sheet
• Texas Instruments,TPS6124x 3.5-MHz High Efficiency Step-Up Converter Data Sheet