SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Table 3-382 shows the PRCM registers and bits which functionality is not supported in this device. Within all PRCM "Register Description" sections the non-functional bits are shaded.
Register/Field/Value | Register/Field/Value | Register/Field/Value |
---|---|---|
CM_DIV_M3_DPLL_CORE_RESTORE | PM_DSS_DSS_WKDEP[29]WKUPDEP_DSI1_B_EVE4 | PM_L4PER_TIMER2_WKDEP[8]WKUPDEP_TIMER2_EVE3 |
CM_DIV_H11_DPLL_CORE_RESTORE | PM_DSS_DSS_WKDEP[28]WKUPDEP_DSI1_B_EVE3 | PM_L4PER_TIMER2_WKDEP[7]WKUPDEP_TIMER2_EVE2 |
CM_DIV_H21_DPLL_CORE_RESTORE | PM_DSS_DSS_WKDEP[27]WKUPDEP_DSI1_B_EVE2 | PM_L4PER_TIMER2_WKDEP[6]WKUPDEP_TIMER2_EVE1 |
CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE | PM_DSS_DSS_WKDEP[26]WKUPDEP_DSI1_B_EVE1 | PM_L4PER_TIMER2_WKDEP[5]WKUPDEP_TIMER2_DSP2 |
CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE | PM_DSS_DSS_WKDEP[25]WKUPDEP_DSI1_B_DSP2 | PM_L4PER_TIMER3_WKDEP[9]WKUPDEP_TIMER3_EVE4 |
CM_CAM_CLKSTCTRL[10]CLKACTIVITY_VIP3_GCLK | PM_DSS_DSS_WKDEP[19]WKUPDEP_DSI1_A_EVE4 | PM_L4PER_TIMER3_WKDEP[8]WKUPDEP_TIMER3_EVE3 |
CM_CAM_STATICDEP[22]EVE4_STATDEP | PM_DSS_DSS_WKDEP[18]WKUPDEP_DSI1_A_EVE3 | PM_L4PER_TIMER3_WKDEP[7]WKUPDEP_TIMER3_EVE2 |
CM_CAM_STATICDEP[21]EVE3_STATDEP | PM_DSS_DSS_WKDEP[17]WKUPDEP_DSI1_A_EVE2 | PM_L4PER_TIMER3_WKDEP[6]WKUPDEP_TIMER3_EVE1 |
CM_CAM_STATICDEP[20]EVE2_STATDEP | PM_DSS_DSS_WKDEP[16]WKUPDEP_DSI1_A_EVE1 | PM_L4PER_TIMER3_WKDEP[5]WKUPDEP_TIMER3_DSP2 |
CM_CAM_STATICDEP[19]EVE1_STATDEP | PM_DSS_DSS_WKDEP[15]WKUPDEP_DSI1_A_DSP2 | PM_L4PER_TIMER4_WKDEP[9]WKUPDEP_TIMER4_EVE4 |
CM_CAM_VIP3_CLKCTRL | PM_DSS_DSS_WKDEP[9]WKUPDEP_DISPC_EVE4 | PM_L4PER_TIMER4_WKDEP[8]WKUPDEP_TIMER4_EVE3 |
CM_CAM_CSI1_CLKCTRL | PM_DSS_DSS_WKDEP[8]WKUPDEP_DISPC_EVE3 | PM_L4PER_TIMER4_WKDEP[7]WKUPDEP_TIMER4_EVE2 |
CM_CAM_CSI2_CLKCTRL | PM_DSS_DSS_WKDEP[7]WKUPDEP_DISPC_EVE2 | PM_L4PER_TIMER4_WKDEP[6]WKUPDEP_TIMER4_EVE1 |
PM_CAM_VIP1_WKDEP[9]WKUPDEP_VIP1_EVE4 | PM_DSS_DSS_WKDEP[6]WKUPDEP_DISPC_EVE1 | PM_L4PER_TIMER4_WKDEP[5]WKUPDEP_TIMER4_DSP2 |
PM_CAM_VIP1_WKDEP[8]WKUPDEP_VIP1_EVE3 | PM_DSS_DSS_WKDEP[5]WKUPDEP_DISPC_DSP2 | PM_L4PER_TIMER9_WKDEP[9]WKUPDEP_TIMER9_EVE4 |
PM_CAM_VIP1_WKDEP[7]WKUPDEP_VIP1_EVE2 | PM_DSS_DSS2_WKDEP[25]WKUPDEP_HDMIDMA_DSP2 | PM_L4PER_TIMER9_WKDEP[8]WKUPDEP_TIMER9_EVE3 |
PM_CAM_VIP1_WKDEP[6]WKUPDEP_VIP1_EVE1 | PM_DSS_DSS2_WKDEP[19]WKUPDEP_DSI1_C_EVE4 | PM_L4PER_TIMER9_WKDEP[7]WKUPDEP_TIMER9_EVE2 |
PM_CAM_VIP1_WKDEP[5]WKUPDEP_VIP1_DSP2 | PM_DSS_DSS2_WKDEP[18]WKUPDEP_DSI1_C_EVE3 | PM_L4PER_TIMER9_WKDEP[6]WKUPDEP_TIMER9_EVE1 |
PM_CAM_CAL_WKDEP[9]WKUPDEP_VIP2_EVE4 | PM_DSS_DSS2_WKDEP[17]WKUPDEP_DSI1_C_EVE2 | PM_L4PER_TIMER9_WKDEP[5]WKUPDEP_TIMER9_DSP2 |
PM_CAM_CAL_WKDEP[8]WKUPDEP_VIP2_EVE3 | PM_DSS_DSS2_WKDEP[16]WKUPDEP_DSI1_C_EVE1 | PM_L4PER_GPIO2_WKDEP[19]WKUPDEP_GPIO2_IRQ2_EVE4 |
PM_CAM_CAL_WKDEP[7]WKUPDEP_VIP2_EVE2 | PM_DSS_DSS2_WKDEP[15]WKUPDEP_DSI1_C_DSP2 | PM_L4PER_GPIO2_WKDEP[18]WKUPDEP_GPIO2_IRQ2_EVE3 |
PM_CAM_CAL_WKDEP[6]WKUPDEP_VIP2_EVE1 | PM_DSS_DSS2_WKDEP[9]WKUPDEP_HDMIIRQ_EVE4 | PM_L4PER_GPIO2_WKDEP[17]WKUPDEP_GPIO2_IRQ2_EVE2 |
PM_CAM_CAL_WKDEP[5]WKUPDEP_VIP2_DSP2 | PM_DSS_DSS2_WKDEP[8]WKUPDEP_HDMIIRQ_EVE3 | PM_L4PER_GPIO2_WKDEP[16]WKUPDEP_GPIO2_IRQ2_EVE1 |
PM_CAM_VIP3_WKDEP | PM_DSS_DSS2_WKDEP[7]WKUPDEP_HDMIIRQ_EVE2 | PM_L4PER_GPIO2_WKDEP[15]WKUPDEP_GPIO2_IRQ2_DSP2 |
RM_CAM_VIP3_CONTEXT | PM_DSS_DSS2_WKDEP[6]WKUPDEP_HDMIIRQ_EVE1 | PM_L4PER_GPIO2_WKDEP[9]WKUPDEP_GPIO2_IRQ1_EVE4 |
RM_CAM_CSI1_CONTEXT | PM_DSS_DSS2_WKDEP[5]WKUPDEP_HDMIIRQ_DSP2 | PM_L4PER_GPIO2_WKDEP[8]WKUPDEP_GPIO2_IRQ1_EVE3 |
RM_CAM_CSI2_CONTEXT | RM_DSS_SDVENC_CONTEXT | PM_L4PER_GPIO2_WKDEP[7]WKUPDEP_GPIO2_IRQ1_EVE2 |
CM_CLKSEL_SYS_CLK1_32K | PM_IPU_MCASP1_WKDEP[15]WKUPDEP_MCASP1_DMA_DSP2 | PM_L4PER_GPIO2_WKDEP[6]WKUPDEP_GPIO2_IRQ1_EVE1 |
CM_CLKSEL_VIDEO2_MCASP_AUX | PM_IPU_MCASP1_WKDEP[9]WKUPDEP_MCASP1_IRQ_EVE4 | PM_L4PER_GPIO2_WKDEP[5]WKUPDEP_GPIO2_IRQ1_DSP2 |
CM_CLKSEL_VIDEO2_TIMER | PM_IPU_MCASP1_WKDEP[8]WKUPDEP_MCASP1_IRQ_EVE3 | PM_L4PER_GPIO3_WKDEP[19]WKUPDEP_GPIO3_IRQ2_EVE4 |
CM_CLKSEL_VIDEO2_PLL_SYS | PM_IPU_MCASP1_WKDEP[7]WKUPDEP_MCASP1_IRQ_EVE2 | PM_L4PER_GPIO3_WKDEP[18]WKUPDEP_GPIO3_IRQ2_EVE3 |
CM_CLKSEL_EVE_CLK | PM_IPU_MCASP1_WKDEP[6]WKUPDEP_MCASP1_IRQ_EVE1 | PM_L4PER_GPIO3_WKDEP[17]WKUPDEP_GPIO3_IRQ2_EVE2 |
CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX | PM_IPU_MCASP1_WKDEP[5]WKUPDEP_MCASP1_IRQ_DSP2 | PM_L4PER_GPIO3_WKDEP[16]WKUPDEP_GPIO3_IRQ2_EVE1 |
CM_CLKSEL_ADC_GFCLK | PM_IPU_TIMER5_WKDEP[9]WKUPDEP_TIMER5_EVE4 | PM_L4PER_GPIO3_WKDEP[15]WKUPDEP_GPIO3_IRQ2_DSP2 |
CM_CLKSEL_EVE_GFCLK_CLKOUTMUX | PM_IPU_TIMER5_WKDEP[8]WKUPDEP_TIMER5_EVE3 | PM_L4PER_GPIO3_WKDEP[9]WKUPDEP_GPIO3_IRQ1_EVE4 |
PM_L3MAIN1_OCMC_RAM2_WKDEP | PM_IPU_TIMER5_WKDEP[7]WKUPDEP_TIMER5_EVE2 | PM_L4PER_GPIO3_WKDEP[8]WKUPDEP_GPIO3_IRQ1_EVE3 |
RM_L3MAIN1_OCMC_RAM2_CONTEXT | PM_IPU_TIMER5_WKDEP[6]WKUPDEP_TIMER5_EVE1 | PM_L4PER_GPIO3_WKDEP[7]WKUPDEP_GPIO3_IRQ1_EVE2 |
PM_L3MAIN1_OCMC_RAM3_WKDEP | PM_IPU_TIMER5_WKDEP[5]WKUPDEP_TIMER5_DSP2 | PM_L4PER_GPIO3_WKDEP[6]WKUPDEP_GPIO3_IRQ1_EVE1 |
RM_L3MAIN1_OCMC_RAM3_CONTEXT | PM_IPU_TIMER6_WKDEP[9]WKUPDEP_TIMER6_EVE4 | PM_L4PER_GPIO3_WKDEP[5]WKUPDEP_GPIO3_IRQ1_DSP2 |
RM_L3MAIN1_OCMC_ROM_CONTEXT | PM_IPU_TIMER6_WKDEP[8]WKUPDEP_TIMER6_EVE3 | PM_L4PER_GPIO4_WKDEP[19]WKUPDEP_GPIO4_IRQ2_EVE4 |
RM_L3MAIN1_SPARE_CME_CONTEXT | PM_IPU_TIMER6_WKDEP[7]WKUPDEP_TIMER6_EVE2 | PM_L4PER_GPIO4_WKDEP[18]WKUPDEP_GPIO4_IRQ2_EVE3 |
RM_L3MAIN1_SPARE_HDMI_CONTEXT | PM_IPU_TIMER6_WKDEP[6]WKUPDEP_TIMER6_EVE1 | PM_L4PER_GPIO4_WKDEP[17]WKUPDEP_GPIO4_IRQ2_EVE2 |
RM_L3MAIN1_SPARE_ICM_CONTEXT | PM_IPU_TIMER6_WKDEP[5]WKUPDEP_TIMER6_DSP2 | PM_L4PER_GPIO4_WKDEP[16]WKUPDEP_GPIO4_IRQ2_EVE1 |
RM_L3MAIN1_SPARE_IVA2_CONTEXT | PM_IPU_TIMER7_WKDEP[9]WKUPDEP_TIMER7_EVE4 | PM_L4PER_GPIO4_WKDEP[15]WKUPDEP_GPIO4_IRQ2_DSP2 |
RM_L3MAIN1_SPARE_SATA2_CONTEXT | PM_IPU_TIMER7_WKDEP[8]WKUPDEP_TIMER7_EVE3 | PM_L4PER_GPIO4_WKDEP[9]WKUPDEP_GPIO4_IRQ1_EVE4 |
RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT | PM_IPU_TIMER7_WKDEP[7]WKUPDEP_TIMER7_EVE2 | PM_L4PER_GPIO4_WKDEP[8]WKUPDEP_GPIO4_IRQ1_EVE3 |
RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT | PM_IPU_TIMER7_WKDEP[6]WKUPDEP_TIMER7_EVE1 | PM_L4PER_GPIO4_WKDEP[7]WKUPDEP_GPIO4_IRQ1_EVE2 |
RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT | PM_IPU_TIMER7_WKDEP[5]WKUPDEP_TIMER7_DSP2 | PM_L4PER_GPIO4_WKDEP[6]WKUPDEP_GPIO4_IRQ1_EVE1 |
RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT | PM_IPU_TIMER8_WKDEP[9]WKUPDEP_TIMER8_EVE4 | PM_L4PER_GPIO4_WKDEP[5]WKUPDEP_GPIO4_IRQ1_DSP2 |
RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT | PM_IPU_TIMER8_WKDEP[8]WKUPDEP_TIMER8_EVE3 | CM_DSP2_CLKSTCTRL |
RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT | PM_IPU_TIMER8_WKDEP[7]WKUPDEP_TIMER8_EVE2 | CM_DSP2_STATICDEP |
RM_EMIF_EMIF2_CONTEXT | PM_IPU_TIMER8_WKDEP[6]WKUPDEP_TIMER8_EVE1 | CM_DSP2_DYNAMICDEP |
RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT | PM_IPU_TIMER8_WKDEP[5]WKUPDEP_TIMER8_DSP2 | CM_DSP2_DSP2_CLKCTRL |
RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT | PM_IPU_I2C5_WKDEP[15]WKUPDEP_I2C5_DMA_DSP2 | CM_EVE1_CLKSTCTRL |
RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT | PM_IPU_I2C5_WKDEP[9]WKUPDEP_I2C5_IRQ_EVE4 | CM_EVE1_STATICDEP |
RM_L4CFG_IO_DELAY_BLOCK_CONTEXT | PM_IPU_I2C5_WKDEP[8]WKUPDEP_I2C5_IRQ_EVE3 | CM_EVE1_EVE1_CLKCTRL |
PM_L3MAIN1_OCMC_RAM1_WKDEP[9]WKUPDEP_OCMC_RAM1_EVE4 | PM_IPU_I2C5_WKDEP[7]WKUPDEP_I2C5_IRQ_EVE2 | CM_EVE2_CLKSTCTRL |
PM_L3MAIN1_OCMC_RAM1_WKDEP[8]WKUPDEP_OCMC_RAM1_EVE3 | PM_IPU_I2C5_WKDEP[6]WKUPDEP_I2C5_IRQ_EVE1 | CM_EVE2_STATICDEP |
PM_L3MAIN1_OCMC_RAM1_WKDEP[7]WKUPDEP_OCMC_RAM1_EVE2 | PM_IPU_I2C5_WKDEP[5]WKUPDEP_I2C5_IRQ_DSP2 | CM_EVE2_EVE2_CLKCTRL |
PM_L3MAIN1_OCMC_RAM1_WKDEP[6]WKUPDEP_OCMC_RAM1_EVE1 | PM_IPU_UART6_WKDEP[9]WKUPDEP_UART6_EVE4 | CM_EVE3_CLKSTCTRL |
PM_L3MAIN1_OCMC_RAM1_WKDEP[5]WKUPDEP_OCMC_RAM1_DSP2 | PM_IPU_UART6_WKDEP[8]WKUPDEP_UART6_EVE3 | CM_EVE3_STATICDEP |
PM_L3MAIN1_TPCC_WKDEP[9]WKUPDEP_TPCC_EVE4 | PM_IPU_UART6_WKDEP[7]WKUPDEP_UART6_EVE2 | CM_EVE3_EVE3_CLKCTRL |
PM_L3MAIN1_TPCC_WKDEP[8]WKUPDEP_TPCC_EVE3 | PM_IPU_UART6_WKDEP[6]WKUPDEP_UART6_EVE1 | CM_EVE4_CLKSTCTRL |
PM_L3MAIN1_TPCC_WKDEP[7]WKUPDEP_TPCC_EVE2 | PM_IPU_UART6_WKDEP[5]WKUPDEP_UART6_DSP2 | CM_EVE4_STATICDEP |
PM_L3MAIN1_TPCC_WKDEP[6]WKUPDEP_TPCC_EVE1 | PM_L3INIT_MMC1_WKDEP[9]WKUPDEP_MMC1_EVE4 | CM_EVE4_EVE4_CLKCTRL |
PM_L3MAIN1_TPCC_WKDEP[5]WKUPDEP_TPCC_DSP2 | PM_L3INIT_MMC1_WKDEP[8]WKUPDEP_MMC1_EVE3 | SRCONFIG |
PRM_VOLTCTRL | PM_L3INIT_MMC1_WKDEP[7]WKUPDEP_MMC1_EVE2 | SRSTATUS |
PRM_PWRREQCTRL | PM_L3INIT_MMC1_WKDEP[6]WKUPDEP_MMC1_EVE1 | SENVAL |
PRM_VOLTSETUP_WARMRESET | PM_L3INIT_MMC1_WKDEP[5]WKUPDEP_MMC1_DSP2 | SENMIN |
PRM_VOLTSETUP_CORE_OFF | PM_L3INIT_MMC2_WKDEP[9]WKUPDEP_MMC2_EVE4 | SENMAX |
PRM_VOLTSETUP_MPU_OFF | PM_L3INIT_MMC2_WKDEP[8]WKUPDEP_MMC2_EVE3 | SENAVG |
PRM_VOLTSETUP_MM_OFF | PM_L3INIT_MMC2_WKDEP[7]WKUPDEP_MMC2_EVE2 | AVGWEIGHT |
PRM_VOLTSETUP_CORE_RET_SLEEP | PM_L3INIT_MMC2_WKDEP[6]WKUPDEP_MMC2_EVE1 | NVALUERECIPROCAL |
PRM_VOLTSETUP_MPU_RET_SLEEP | PM_L3INIT_MMC2_WKDEP[5]WKUPDEP_MMC2_DSP2 | IRQ_EOI |
PRM_VOLTSETUP_MM_RET_SLEEP | PM_L3INIT_USB_OTG_SS2_WKDEP[9]WKUPDEP_USB_OTG_SS2_EVE4 | IRQSTATUS_RAW |
PRM_VP_CORE_CONFIG | PM_L3INIT_USB_OTG_SS2_WKDEP[8]WKUPDEP_USB_OTG_SS2_EVE3 | IRQSTATUS |
PRM_VP_CORE_STATUS | PM_L3INIT_USB_OTG_SS2_WKDEP[7]WKUPDEP_USB_OTG_SS2_EVE2 | IRQENABLE_SET |
PRM_VP_CORE_VLIMITTO | PM_L3INIT_USB_OTG_SS2_WKDEP[6]WKUPDEP_USB_OTG_SS2_EVE1 | IRQENABLE_CLR |
PRM_VP_CORE_VOLTAGE | PM_L3INIT_USB_OTG_SS2_WKDEP[5]WKUPDEP_USB_OTG_SS2_DSP2 | SENERROR |
PRM_VP_CORE_VSTEPMAX | PM_L3INIT_USB_OTG_SS3_WKDEP[9]WKUPDEP_USB_OTG_SS3_EVE4 | ERRCONFIG |
PRM_VP_CORE_VSTEPMIN | PM_L3INIT_USB_OTG_SS3_WKDEP[8]WKUPDEP_USB_OTG_SS3_EVE3 | PM_COREAON_SMARTREFLEX_MPU_WKDEP |
PRM_VP_MPU_CONFIG | PM_L3INIT_USB_OTG_SS3_WKDEP[7]WKUPDEP_USB_OTG_SS3_EVE2 | RM_COREAON_SMARTREFLEX_MPU_CONTEXT |
PRM_VP_MPU_STATUS | PM_L3INIT_USB_OTG_SS3_WKDEP[6]WKUPDEP_USB_OTG_SS3_EVE1 | PM_COREAON_SMARTREFLEX_CORE_WKDEP |
PRM_VP_MPU_VLIMITTO | PM_L3INIT_USB_OTG_SS3_WKDEP[5]WKUPDEP_USB_OTG_SS3_DSP2 | RM_COREAON_SMARTREFLEX_CORE_CONTEXT |
PRM_VP_MPU_VOLTAGE | PM_L3INIT_USB_OTG_SS4_WKDEP | PM_COREAON_SMARTREFLEX_GPU_WKDEP |
PRM_VP_MPU_VSTEPMAX | RM_L3INIT_USB_OTG_SS4_CONTEXT | RM_COREAON_SMARTREFLEX_GPU_CONTEXT |
PRM_VP_MPU_VSTEPMIN | PM_L3INIT_SATA_WKDEP[9]WKUPDEP_SATA_EVE4 | PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP |
PRM_VP_MM_CONFIG | PM_L3INIT_SATA_WKDEP[8]WKUPDEP_SATA_EVE3 | RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT |
PRM_VP_MM_STATUS | PM_L3INIT_SATA_WKDEP[7]WKUPDEP_SATA_EVE2 | PM_COREAON_SMARTREFLEX_IVAHD_WKDEP |
PRM_VP_MM_VLIMITTO | PM_L3INIT_SATA_WKDEP[6]WKUPDEP_SATA_EVE1 | RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT |
PRM_VP_MM_VOLTAGE | PM_L3INIT_SATA_WKDEP[5]WKUPDEP_SATA_DSP2 | RM_COREAON_DUMMY_MODULE1_CONTEXT |
PRM_VP_MM_VSTEPMAX | PM_PCIE_PCIESS1_WKDEP[9]WKUPDEP_PCIESS1_EVE4 | RM_COREAON_DUMMY_MODULE2_CONTEXT |
PRM_VP_MM_VSTEPMIN | PM_PCIE_PCIESS1_WKDEP[8]WKUPDEP_PCIESS1_EVE3 | RM_COREAON_DUMMY_MODULE3_CONTEXT |
PRM_VC_SMPS_CORE_CONFIG | PM_PCIE_PCIESS1_WKDEP[7]WKUPDEP_PCIESS1_EVE2 | RM_COREAON_DUMMY_MODULE4_CONTEXT |
PRM_VC_SMPS_MM_CONFIG | PM_PCIE_PCIESS1_WKDEP[6]WKUPDEP_PCIESS1_EVE1 | PM_DSP2_PWRSTCTRL |
PRM_VC_SMPS_MPU_CONFIG | PM_PCIE_PCIESS1_WKDEP[5]WKUPDEP_PCIESS1_DSP2 | PM_DSP2_PWRSTST |
PRM_VC_VAL_CMD_VDD_CORE_L | PM_PCIE_PCIESS2_WKDEP[9]WKUPDEP_PCIESS2_EVE4 | RM_DSP2_RSTCTRL |
PRM_VC_VAL_CMD_VDD_MM_L | PM_PCIE_PCIESS2_WKDEP[8]WKUPDEP_PCIESS2_EVE3 | RM_DSP2_RSTST |
PRM_VC_VAL_CMD_VDD_MPU_L | PM_PCIE_PCIESS2_WKDEP[7]WKUPDEP_PCIESS2_EVE2 | RM_DSP2_DSP2_CONTEXT |
PRM_VC_VAL_BYPASS | PM_PCIE_PCIESS2_WKDEP[6]WKUPDEP_PCIESS2_EVE1 | PM_EVE1_PWRSTCTRL |
PRM_VC_CORE_ERRST | PM_PCIE_PCIESS2_WKDEP[5]WKUPDEP_PCIESS2_DSP2 | PM_EVE1_PWRSTST |
PRM_VC_MM_ERRST | PM_L3INIT_USB_OTG_SS1_WKDEP[9]WKUPDEP_USB_OTG_SS1_EVE4 | RM_EVE1_RSTCTRL |
PRM_VC_MPU_ERRST | PM_L3INIT_USB_OTG_SS1_WKDEP[8]WKUPDEP_USB_OTG_SS1_EVE3 | RM_EVE1_RSTST |
PRM_VC_BYPASS_ERRST | PM_L3INIT_USB_OTG_SS1_WKDEP[7]WKUPDEP_USB_OTG_SS1_EVE2 | PM_EVE1_EVE1_WKDEP |
PRM_VC_CFG_I2C_MODE | PM_L3INIT_USB_OTG_SS1_WKDEP[6]WKUPDEP_USB_OTG_SS1_EVE1 | RM_EVE1_EVE1_CONTEXT |
PRM_VC_CFG_I2C_CLK | PM_L3INIT_USB_OTG_SS1_WKDEP[5]WKUPDEP_USB_OTG_SS1_DSP2 | PM_EVE2_PWRSTCTRL |
PRM_SRAM_WKUP_SETUP | PM_L4PER_TIMER10_WKDEP[9]WKUPDEP_TIMER10_EVE4 | PM_EVE2_PWRSTST |
PRM_DEVICE_OFF_CTRL | PM_L4PER_TIMER10_WKDEP[8]WKUPDEP_TIMER10_EVE3 | RM_EVE2_RSTCTRL |
PRM_MODEM_IF_CTRL | PM_L4PER_TIMER10_WKDEP[7]WKUPDEP_TIMER10_EVE2 | RM_EVE2_RSTST |
PRM_VOLTST_MPU | PM_L4PER_TIMER10_WKDEP[6]WKUPDEP_TIMER10_EVE1 | PM_EVE2_EVE2_WKDEP |
PRM_VOLTST_MM | PM_L4PER_TIMER10_WKDEP[5]WKUPDEP_TIMER10_DSP2 | RM_EVE2_EVE2_CONTEXT |
PRM_RSTST[14]LLI_RST | PM_L4PER_TIMER11_WKDEP[9]WKUPDEP_TIMER11_EVE4 | PM_EVE3_PWRSTCTRL |
PRM_RSTST[10]C2C_RST | PM_L4PER_TIMER11_WKDEP[8]WKUPDEP_TIMER11_EVE3 | PM_EVE3_PWRSTST |
PRM_RSTST[8]VDD_CORE_VOLT_MGR_RST | PM_L4PER_TIMER11_WKDEP[7]WKUPDEP_TIMER11_EVE2 | RM_EVE3_RSTCTRL |
PRM_RSTST[7]VDD_MM_VOLT_MGR_RST | PM_L4PER_TIMER11_WKDEP[6]WKUPDEP_TIMER11_EVE1 | RM_EVE3_RSTST |
PRM_RSTST[6]VDD_MPU_VOLT_MGR_RST | PM_L4PER_TIMER11_WKDEP[5]WKUPDEP_TIMER11_DSP2 | PM_EVE3_EVE3_WKDEP |
PRM_RSTST[4]SECURE_WDT_RST | PM_L4PER_TIMER2_WKDEP[9]WKUPDEP_TIMER2_EVE4 | RM_EVE3_EVE3_CONTEXT |
PRM_RSTST[2]MPU_SECURITY_VIOL_RST | PM_L4PER_TIMER14_WKDEP[9]WKUPDEP_TIMER14_EVE4 | PM_EVE4_PWRSTCTRL |
PM_L4PER_GPIO5_WKDEP[19]WKUPDEP_GPIO5_IRQ2_EVE4 | PM_L4PER_TIMER14_WKDEP[8]WKUPDEP_TIMER14_EVE3 | PM_EVE4_PWRSTST |
PM_L4PER_GPIO5_WKDEP[18]WKUPDEP_GPIO5_IRQ2_EVE3 | PM_L4PER_TIMER14_WKDEP[7]WKUPDEP_TIMER14_EVE2 | RM_EVE4_RSTCTRL |
PM_L4PER_GPIO5_WKDEP[17]WKUPDEP_GPIO5_IRQ2_EVE2 | PM_L4PER_TIMER14_WKDEP[6]WKUPDEP_TIMER14_EVE1 | RM_EVE4_RSTST |
PM_L4PER_GPIO5_WKDEP[16]WKUPDEP_GPIO5_IRQ2_EVE1 | PM_L4PER_TIMER14_WKDEP[5]WKUPDEP_TIMER14_DSP2 | PM_EVE4_EVE4_WKDEP |
PM_L4PER_GPIO5_WKDEP[15]WKUPDEP_GPIO5_IRQ2_DSP2 | PM_L4PER_TIMER15_WKDEP[9]WKUPDEP_TIMER15_EVE4 | RM_EVE4_EVE4_CONTEXT |
PM_L4PER_GPIO5_WKDEP[9]WKUPDEP_GPIO5_IRQ1_EVE4 | PM_L4PER_TIMER15_WKDEP[8]WKUPDEP_TIMER15_EVE3 | PM_L4PER_GPIO8_WKDEP[5]WKUPDEP_GPIO8_IRQ1_DSP2 |
PM_L4PER_GPIO5_WKDEP[8]WKUPDEP_GPIO5_IRQ1_EVE3 | PM_L4PER_TIMER15_WKDEP[7]WKUPDEP_TIMER15_EVE2 | PM_L4PER_MMC3_WKDEP[9]WKUPDEP_MMC3_EVE4 |
PM_L4PER_GPIO5_WKDEP[7]WKUPDEP_GPIO5_IRQ1_EVE2 | PM_L4PER_TIMER15_WKDEP[6]WKUPDEP_TIMER15_EVE1 | PM_L4PER_MMC3_WKDEP[8]WKUPDEP_MMC3_EVE3 |
PM_L4PER_GPIO5_WKDEP[6]WKUPDEP_GPIO5_IRQ1_EVE1 | PM_L4PER_TIMER15_WKDEP[5]WKUPDEP_TIMER15_DSP2 | PM_L4PER_MMC3_WKDEP[7]WKUPDEP_MMC3_EVE2 |
PM_L4PER_GPIO5_WKDEP[5]WKUPDEP_GPIO5_IRQ1_DSP2 | PM_L4PER_MCSPI1_WKDEP[9]WKUPDEP_MCSPI1_EVE4 | PM_L4PER_MMC3_WKDEP[6]WKUPDEP_MMC3_EVE1 |
PM_L4PER_GPIO6_WKDEP[19]WKUPDEP_GPIO6_IRQ2_EVE4 | PM_L4PER_MCSPI1_WKDEP[8]WKUPDEP_MCSPI1_EVE3 | PM_L4PER_MMC3_WKDEP[5]WKUPDEP_MMC3_DSP2 |
PM_L4PER_GPIO6_WKDEP[18]WKUPDEP_GPIO6_IRQ2_EVE3 | PM_L4PER_MCSPI1_WKDEP[7]WKUPDEP_MCSPI1_EVE2 | PM_L4PER_MMC4_WKDEP[9]WKUPDEP_MMC4_EVE4 |
PM_L4PER_GPIO6_WKDEP[17]WKUPDEP_GPIO6_IRQ2_EVE2 | PM_L4PER_MCSPI1_WKDEP[6]WKUPDEP_MCSPI1_EVE1 | PM_L4PER_MMC4_WKDEP[8]WKUPDEP_MMC4_EVE3 |
PM_L4PER_GPIO6_WKDEP[16]WKUPDEP_GPIO6_IRQ2_EVE1 | PM_L4PER_MCSPI1_WKDEP[5]WKUPDEP_MCSPI1_DSP2 | PM_L4PER_MMC4_WKDEP[7]WKUPDEP_MMC4_EVE2 |
PM_L4PER_GPIO6_WKDEP[15]WKUPDEP_GPIO6_IRQ2_DSP2 | PM_L4PER_MCSPI2_WKDEP[9]WKUPDEP_MCSPI2_EVE4 | PM_L4PER_MMC4_WKDEP[6]WKUPDEP_MMC4_EVE1 |
PM_L4PER_GPIO6_WKDEP[9]WKUPDEP_GPIO6_IRQ1_EVE4 | PM_L4PER_MCSPI2_WKDEP[8]WKUPDEP_MCSPI2_EVE3 | PM_L4PER_MMC4_WKDEP[5]WKUPDEP_MMC4_DSP2 |
PM_L4PER_GPIO6_WKDEP[8]WKUPDEP_GPIO6_IRQ1_EVE3 | PM_L4PER_MCSPI2_WKDEP[7]WKUPDEP_MCSPI2_EVE2 | PM_L4PER_TIMER16_WKDEP[9]WKUPDEP_TIMER16_EVE4 |
PM_L4PER_GPIO6_WKDEP[7]WKUPDEP_GPIO6_IRQ1_EVE2 | PM_L4PER_MCSPI2_WKDEP[6]WKUPDEP_MCSPI2_EVE1 | PM_L4PER_TIMER16_WKDEP[8]WKUPDEP_TIMER16_EVE3 |
PM_L4PER_GPIO6_WKDEP[6]WKUPDEP_GPIO6_IRQ1_EVE1 | PM_L4PER_MCSPI2_WKDEP[5]WKUPDEP_MCSPI2_DSP2 | PM_L4PER_TIMER16_WKDEP[7]WKUPDEP_TIMER16_EVE2 |
PM_L4PER_GPIO6_WKDEP[5]WKUPDEP_GPIO6_IRQ1_DSP2 | PM_L4PER_MCSPI3_WKDEP[9]WKUPDEP_MCSPI3_EVE4 | PM_L4PER_TIMER16_WKDEP[6]WKUPDEP_TIMER16_EVE1 |
PM_L4PER_I2C1_WKDEP[15]WKUPDEP_I2C1_DMA_DSP2 | PM_L4PER_MCSPI3_WKDEP[8]WKUPDEP_MCSPI3_EVE3 | PM_L4PER_TIMER16_WKDEP[5]WKUPDEP_TIMER16_DSP2 |
PM_L4PER_I2C1_WKDEP[9]WKUPDEP_I2C1_IRQ_EVE4 | PM_L4PER_MCSPI3_WKDEP[7]WKUPDEP_MCSPI3_EVE2 | PM_L4PER2_QSPI_WKDEP[9]WKUPDEP_QSPI_EVE4 |
PM_L4PER_I2C1_WKDEP[8]WKUPDEP_I2C1_IRQ_EVE3 | PM_L4PER_MCSPI3_WKDEP[6]WKUPDEP_MCSPI3_EVE1 | PM_L4PER2_QSPI_WKDEP[8]WKUPDEP_QSPI_EVE3 |
PM_L4PER_I2C1_WKDEP[7]WKUPDEP_I2C1_IRQ_EVE2 | PM_L4PER_MCSPI3_WKDEP[5]WKUPDEP_MCSPI3_DSP2 | PM_L4PER2_QSPI_WKDEP[7]WKUPDEP_QSPI_EVE2 |
PM_L4PER_I2C1_WKDEP[6]WKUPDEP_I2C1_IRQ_EVE1 | PM_L4PER_MCSPI4_WKDEP[9]WKUPDEP_MCSPI4_EVE4 | PM_L4PER2_QSPI_WKDEP[6]WKUPDEP_QSPI_EVE1 |
PM_L4PER_I2C1_WKDEP[5]WKUPDEP_I2C1_IRQ_DSP2 | PM_L4PER_MCSPI4_WKDEP[8]WKUPDEP_MCSPI4_EVE3 | PM_L4PER2_QSPI_WKDEP[5]WKUPDEP_QSPI_DSP2 |
PM_L4PER_I2C2_WKDEP[15]WKUPDEP_I2C2_DMA_DSP2 | PM_L4PER_MCSPI4_WKDEP[7]WKUPDEP_MCSPI4_EVE2 | PM_L4PER_UART1_WKDEP[9]WKUPDEP_UART1_EVE4 |
PM_L4PER_I2C2_WKDEP[9]WKUPDEP_I2C2_IRQ_EVE4 | PM_L4PER_MCSPI4_WKDEP[6]WKUPDEP_MCSPI4_EVE1 | PM_L4PER_UART1_WKDEP[8]WKUPDEP_UART1_EVE3 |
PM_L4PER_I2C2_WKDEP[8]WKUPDEP_I2C2_IRQ_EVE3 | PM_L4PER_MCSPI4_WKDEP[5]WKUPDEP_MCSPI4_DSP2 | PM_L4PER_UART1_WKDEP[7]WKUPDEP_UART1_EVE2 |
PM_L4PER_I2C2_WKDEP[7]WKUPDEP_I2C2_IRQ_EVE2 | PM_L4PER_GPIO7_WKDEP[19]WKUPDEP_GPIO7_IRQ2_EVE4 | PM_L4PER_UART1_WKDEP[6]WKUPDEP_UART1_EVE1 |
PM_L4PER_I2C2_WKDEP[6]WKUPDEP_I2C2_IRQ_EVE1 | PM_L4PER_GPIO7_WKDEP[18]WKUPDEP_GPIO7_IRQ2_EVE3 | PM_L4PER_UART1_WKDEP[5]WKUPDEP_UART1_DSP2 |
PM_L4PER_I2C2_WKDEP[5]WKUPDEP_I2C2_IRQ_DSP2 | PM_L4PER_GPIO7_WKDEP[17]WKUPDEP_GPIO7_IRQ2_EVE2 | PM_L4PER_UART2_WKDEP[9]WKUPDEP_UART2_EVE4 |
PM_L4PER_I2C3_WKDEP[15]WKUPDEP_I2C3_DMA_DSP2 | PM_L4PER_GPIO7_WKDEP[16]WKUPDEP_GPIO7_IRQ2_EVE1 | PM_L4PER_UART2_WKDEP[8]WKUPDEP_UART2_EVE3 |
PM_L4PER_I2C3_WKDEP[9]WKUPDEP_I2C3_IRQ_EVE4 | PM_L4PER_GPIO7_WKDEP[15]WKUPDEP_GPIO7_IRQ2_DSP2 | PM_L4PER_UART2_WKDEP[7]WKUPDEP_UART2_EVE2 |
PM_L4PER_I2C3_WKDEP[8]WKUPDEP_I2C3_IRQ_EVE3 | PM_L4PER_GPIO7_WKDEP[9]WKUPDEP_GPIO7_IRQ1_EVE4 | PM_L4PER_UART2_WKDEP[6]WKUPDEP_UART2_EVE1 |
PM_L4PER_I2C3_WKDEP[7]WKUPDEP_I2C3_IRQ_EVE2 | PM_L4PER_GPIO7_WKDEP[8]WKUPDEP_GPIO7_IRQ1_EVE3 | PM_L4PER_UART2_WKDEP[5]WKUPDEP_UART2_DSP2 |
PM_L4PER_I2C3_WKDEP[6]WKUPDEP_I2C3_IRQ_EVE1 | PM_L4PER_GPIO7_WKDEP[7]WKUPDEP_GPIO7_IRQ1_EVE2 | PM_L4PER_UART3_WKDEP[9]WKUPDEP_UART3_EVE4 |
PM_L4PER_I2C3_WKDEP[5]WKUPDEP_I2C3_IRQ_DSP2 | PM_L4PER_GPIO7_WKDEP[6]WKUPDEP_GPIO7_IRQ1_EVE1 | PM_L4PER_UART3_WKDEP[8]WKUPDEP_UART3_EVE3 |
PM_L4PER_I2C4_WKDEP[15]WKUPDEP_I2C4_DMA_DSP2 | PM_L4PER_GPIO7_WKDEP[5]WKUPDEP_GPIO7_IRQ1_DSP2 | PM_L4PER_UART3_WKDEP[7]WKUPDEP_UART3_EVE2 |
PM_L4PER_I2C4_WKDEP[9]WKUPDEP_I2C4_IRQ_EVE4 | PM_L4PER_GPIO8_WKDEP[19]WKUPDEP_GPIO8_IRQ2_EVE4 | PM_L4PER_UART3_WKDEP[6]WKUPDEP_UART3_EVE1 |
PM_L4PER_I2C4_WKDEP[8]WKUPDEP_I2C4_IRQ_EVE3 | PM_L4PER_GPIO8_WKDEP[18]WKUPDEP_GPIO8_IRQ2_EVE3 | PM_L4PER_UART3_WKDEP[5]WKUPDEP_UART3_DSP2 |
PM_L4PER_I2C4_WKDEP[7]WKUPDEP_I2C4_IRQ_EVE2 | PM_L4PER_GPIO8_WKDEP[17]WKUPDEP_GPIO8_IRQ2_EVE2 | PM_L4PER_UART4_WKDEP[9]WKUPDEP_UART4_EVE4 |
PM_L4PER_I2C4_WKDEP[6]WKUPDEP_I2C4_IRQ_EVE1 | PM_L4PER_GPIO8_WKDEP[16]WKUPDEP_GPIO8_IRQ2_EVE1 | PM_L4PER_UART4_WKDEP[8]WKUPDEP_UART4_EVE3 |
PM_L4PER_I2C4_WKDEP[5]WKUPDEP_I2C4_IRQ_DSP2 | PM_L4PER_GPIO8_WKDEP[15]WKUPDEP_GPIO8_IRQ2_DSP2 | PM_L4PER_UART4_WKDEP[7]WKUPDEP_UART4_EVE2 |
PM_L4PER_TIMER13_WKDEP[9]WKUPDEP_TIMER13_EVE4 | PM_L4PER_GPIO8_WKDEP[9]WKUPDEP_GPIO8_IRQ1_EVE4 | PM_L4PER_UART4_WKDEP[6]WKUPDEP_UART4_EVE1 |
PM_L4PER_TIMER13_WKDEP[8]WKUPDEP_TIMER13_EVE3 | PM_L4PER_GPIO8_WKDEP[8]WKUPDEP_GPIO8_IRQ1_EVE3 | PM_L4PER_UART4_WKDEP[5]WKUPDEP_UART4_DSP2 |
PM_L4PER_TIMER13_WKDEP[7]WKUPDEP_TIMER13_EVE2 | PM_L4PER_GPIO8_WKDEP[7]WKUPDEP_GPIO8_IRQ1_EVE2 | PM_L4PER2_MCASP2_WKDEP[15]WKUPDEP_MCASP2_DMA_DSP2 |
PM_L4PER_TIMER13_WKDEP[6]WKUPDEP_TIMER13_EVE1 | PM_L4PER_GPIO8_WKDEP[6]WKUPDEP_GPIO8_IRQ1_EVE1 | PM_L4PER2_MCASP2_WKDEP[9]WKUPDEP_MCASP2_IRQ_EVE4 |
PM_L4PER_TIMER13_WKDEP[5]WKUPDEP_TIMER13_DSP2 | PM_L4PER2_MCASP7_WKDEP[15]WKUPDEP_MCASP7_DMA_DSP2 | PM_L4PER2_MCASP2_WKDEP[8]WKUPDEP_MCASP2_IRQ_EVE3 |
PM_L4PER2_MCASP3_WKDEP[7]WKUPDEP_MCASP3_IRQ_EVE2 | PM_L4PER2_MCASP7_WKDEP[9]WKUPDEP_MCASP7_IRQ_EVE4 | PM_L4PER2_MCASP2_WKDEP[7]WKUPDEP_MCASP2_IRQ_EVE2 |
PM_L4PER2_MCASP3_WKDEP[6]WKUPDEP_MCASP3_IRQ_EVE1 | PM_L4PER2_MCASP7_WKDEP[8]WKUPDEP_MCASP7_IRQ_EVE3 | PM_L4PER2_MCASP2_WKDEP[6]WKUPDEP_MCASP2_IRQ_EVE1 |
PM_L4PER2_MCASP3_WKDEP[5]WKUPDEP_MCASP3_IRQ_DSP2 | PM_L4PER2_MCASP7_WKDEP[7]WKUPDEP_MCASP7_IRQ_EVE2 | PM_L4PER2_MCASP2_WKDEP[5]WKUPDEP_MCASP2_IRQ_DSP2 |
PM_L4PER_UART5_WKDEP[9]WKUPDEP_UART5_EVE4 | PM_L4PER2_MCASP7_WKDEP[6]WKUPDEP_MCASP7_IRQ_EVE1 | PM_L4PER2_MCASP3_WKDEP[15]WKUPDEP_MCASP3_DMA_DSP2 |
PM_L4PER_UART5_WKDEP[8]WKUPDEP_UART5_EVE3 | PM_L4PER2_MCASP7_WKDEP[5]WKUPDEP_MCASP7_IRQ_DSP2 | PM_L4PER2_MCASP3_WKDEP[9]WKUPDEP_MCASP3_IRQ_EVE4 |
PM_L4PER_UART5_WKDEP[7]WKUPDEP_UART5_EVE2 | PM_L4PER2_MCASP8_WKDEP[15]WKUPDEP_MCASP8_DMA_DSP2 | PM_L4PER2_MCASP3_WKDEP[8]WKUPDEP_MCASP3_IRQ_EVE3 |
PM_L4PER_UART5_WKDEP[6]WKUPDEP_UART5_EVE1 | PM_L4PER2_MCASP8_WKDEP[9]WKUPDEP_MCASP8_IRQ_EVE4 | PM_L4PER2_UART7_WKDEP[7]WKUPDEP_UART7_EVE2 |
PM_L4PER_UART5_WKDEP[5]WKUPDEP_UART5_DSP2 | PM_L4PER2_MCASP8_WKDEP[8]WKUPDEP_MCASP8_IRQ_EVE3 | PM_L4PER2_UART7_WKDEP[6]WKUPDEP_UART7_EVE1 |
PM_L4PER2_MCASP5_WKDEP[15]WKUPDEP_MCASP5_DMA_DSP2 | PM_L4PER2_MCASP8_WKDEP[7]WKUPDEP_MCASP8_IRQ_EVE2 | PM_L4PER2_UART7_WKDEP[5]WKUPDEP_UART7_DSP2 |
PM_L4PER2_MCASP5_WKDEP[9]WKUPDEP_MCASP5_IRQ_EVE4 | PM_L4PER2_MCASP8_WKDEP[6]WKUPDEP_MCASP8_IRQ_EVE1 | PM_L4PER2_UART8_WKDEP[9]WKUPDEP_UART8_EVE4 |
PM_L4PER2_MCASP5_WKDEP[8]WKUPDEP_MCASP5_IRQ_EVE3 | PM_L4PER2_MCASP8_WKDEP[5]WKUPDEP_MCASP8_IRQ_DSP2 | PM_L4PER2_UART8_WKDEP[8]WKUPDEP_UART8_EVE3 |
PM_L4PER2_MCASP5_WKDEP[7]WKUPDEP_MCASP5_IRQ_EVE2 | PM_L4PER2_MCASP4_WKDEP[15]WKUPDEP_MCASP4_DMA_DSP2 | PM_L4PER2_UART8_WKDEP[7]WKUPDEP_UART8_EVE2 |
PM_L4PER2_MCASP5_WKDEP[6]WKUPDEP_MCASP5_IRQ_EVE1 | PM_L4PER2_MCASP4_WKDEP[9]WKUPDEP_MCASP4_IRQ_EVE4 | PM_L4PER2_UART8_WKDEP[6]WKUPDEP_UART8_EVE1 |
PM_L4PER2_MCASP5_WKDEP[5]WKUPDEP_MCASP5_IRQ_DSP2 | PM_L4PER2_MCASP4_WKDEP[8]WKUPDEP_MCASP4_IRQ_EVE3 | PM_L4PER2_UART8_WKDEP[5]WKUPDEP_UART8_DSP2 |
PM_L4PER2_MCASP6_WKDEP[15]WKUPDEP_MCASP6_DMA_DSP2 | PM_L4PER2_MCASP4_WKDEP[7]WKUPDEP_MCASP4_IRQ_EVE2 | PM_L4PER2_UART9_WKDEP[9]WKUPDEP_UART9_EVE4 |
PM_L4PER2_MCASP6_WKDEP[9]WKUPDEP_MCASP6_IRQ_EVE4 | PM_L4PER2_MCASP4_WKDEP[6]WKUPDEP_MCASP4_IRQ_EVE1 | PM_L4PER2_UART9_WKDEP[8]WKUPDEP_UART9_EVE3 |
PM_L4PER2_MCASP6_WKDEP[8]WKUPDEP_MCASP6_IRQ_EVE3 | PM_L4PER2_MCASP4_WKDEP[5]WKUPDEP_MCASP4_IRQ_DSP2 | PM_L4PER2_UART9_WKDEP[7]WKUPDEP_UART9_EVE2 |
PM_L4PER2_MCASP6_WKDEP[7]WKUPDEP_MCASP6_IRQ_EVE2 | PM_L4PER2_UART7_WKDEP[9]WKUPDEP_UART7_EVE4 | PM_L4PER2_UART9_WKDEP[6]WKUPDEP_UART9_EVE1 |
PM_L4PER2_MCASP6_WKDEP[6]WKUPDEP_MCASP6_IRQ_EVE1 | PM_L4PER2_UART7_WKDEP[8]WKUPDEP_UART7_EVE3 | PM_L4PER2_UART9_WKDEP[5]WKUPDEP_UART9_DSP2 |
PM_L4PER2_MCASP6_WKDEP[5]WKUPDEP_MCASP6_IRQ_DSP2 | PRM_IRQSTATUS_EVE4 | PM_L4PER2_DCAN2_WKDEP[9]WKUPDEP_DCAN2_EVE4 |
PRM_IRQENABLE_EVE2 | PM_RTC_RTCSS_WKDEP[9]WKUPDEP_RTC_IRQ1_EVE4 | PM_L4PER2_DCAN2_WKDEP[8]WKUPDEP_DCAN2_EVE3 |
PRM_IRQENABLE_EVE3 | PM_RTC_RTCSS_WKDEP[8]WKUPDEP_RTC_IRQ1_EVE3 | PM_L4PER2_DCAN2_WKDEP[7]WKUPDEP_DCAN2_EVE2 |
PRM_IRQENABLE_EVE4 | PM_RTC_RTCSS_WKDEP[7]WKUPDEP_RTC_IRQ1_EVE2 | PM_L4PER2_DCAN2_WKDEP[6]WKUPDEP_DCAN2_EVE1 |
PRM_IRQSTATUS_DSP2 | PM_RTC_RTCSS_WKDEP[6]WKUPDEP_RTC_IRQ1_EVE1 | PM_L4PER2_DCAN2_WKDEP[5]WKUPDEP_DCAN2_DSP2 |
PRM_IRQSTATUS_EVE1 | PM_RTC_RTCSS_WKDEP[5]WKUPDEP_RTC_IRQ1_DSP2 | PRM_IRQENABLE_DSP2 |
PRM_IRQSTATUS_EVE2 | PM_VPE_VPE_WKDEP[9]WKUPDEP_VPE_EVE4 | PRM_IRQENABLE_EVE1 |
PRM_IRQSTATUS_EVE3 | CM_WKUPAON_SPARE_SAFETY4_CLKCTRL | PRM_IRQSTATUS_MPU[12]DPLL_EVE_RECAL_ST |
PRM_IRQSTATUS_IPU1[12]DPLL_EVE_RECAL_ST | CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL | PRM_IRQENABLE_MPU[12]DPLL_EVE_RECAL_EN |
PM_RTC_RTCSS_WKDEP[19]WKUPDEP_RTC_IRQ2_EVE4 | CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL | PRM_IRQSTATUS_IPU2[12]DPLL_EVE_RECAL_ST |
PM_RTC_RTCSS_WKDEP[18]WKUPDEP_RTC_IRQ2_EVE3 | CM_WKUPAON_CLKSTCTRL[19]CLKACTIVITY_ADC_L3_GICLK | PRM_IRQENABLE_IPU2[12]DPLL_EVE_RECAL_EN |
PM_RTC_RTCSS_WKDEP[17]WKUPDEP_RTC_IRQ2_EVE2 | CM_WKUPAON_CLKSTCTRL[13]CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK | PRM_IRQSTATUS_DSP1[12]DPLL_EVE_RECAL_ST |
PM_RTC_RTCSS_WKDEP[16]WKUPDEP_RTC_IRQ2_EVE1 | CM_WKUPAON_CLKSTCTRL[10]CLKACTIVITY_ADC_GFCLK | PRM_IRQENABLE_DSP1[12]DPLL_EVE_RECAL_EN |
PM_RTC_RTCSS_WKDEP[15]WKUPDEP_RTC_IRQ2_DSP2 | PM_WKUPAON_GPIO1_WKDEP[9]WKUPDEP_GPIO1_IRQ1_EVE4 | PRM_IRQENABLE_IPU1[12]DPLL_EVE_RECAL_EN |
CM_WKUPAON_SCRM_CLKCTRL | PM_WKUPAON_GPIO1_WKDEP[8]WKUPDEP_GPIO1_IRQ1_EVE3 | PM_VPE_VPE_WKDEP[8]WKUPDEP_VPE_EVE3 |
CM_WKUPAON_IO_SRCOMP_CLKCTRL | PM_WKUPAON_GPIO1_WKDEP[7]WKUPDEP_GPIO1_IRQ1_EVE2 | PM_VPE_VPE_WKDEP[7]WKUPDEP_VPE_EVE2 |
CM_WKUPAON_ADC_CLKCTRL | PM_WKUPAON_GPIO1_WKDEP[6]WKUPDEP_GPIO1_IRQ1_EVE1 | PM_VPE_VPE_WKDEP[6]WKUPDEP_VPE_EVE1 |
CM_WKUPAON_SPARE_SAFETY1_CLKCTRL | PM_WKUPAON_GPIO1_WKDEP[5]WKUPDEP_GPIO1_IRQ1_DSP2 | PM_VPE_VPE_WKDEP[5]WKUPDEP_VPE_DSP2 |
CM_WKUPAON_SPARE_SAFETY2_CLKCTRL | PM_WKUPAON_TIMER1_WKDEP[9]WKUPDEP_TIMER1_EVE4 | CM_WKUPAON_WD_TIMER1_CLKCTRL |
CM_WKUPAON_SPARE_SAFETY3_CLKCTRL | PM_WKUPAON_TIMER1_WKDEP[8]WKUPDEP_TIMER1_EVE3 | CM_WKUPAON_SAR_RAM_CLKCTRL |
RM_WKUPAON_SPARE_SAFETY1_CONTEXT | PM_WKUPAON_TIMER1_WKDEP[7]WKUPDEP_TIMER1_EVE2 | CM_WKUPAON_TIMER1_CLKCTRL[27:24]CLKSEL=0x9 |
RM_WKUPAON_SPARE_SAFETY2_CONTEXT | PM_WKUPAON_TIMER1_WKDEP[6]WKUPDEP_TIMER1_EVE1 | PM_WKUPAON_WD_TIMER1_WKDEP |
RM_WKUPAON_SPARE_SAFETY3_CONTEXT | PM_WKUPAON_TIMER1_WKDEP[5]WKUPDEP_TIMER1_DSP2 | RM_WKUPAON_WD_TIMER1_CONTEXT |
RM_WKUPAON_SPARE_SAFETY4_CONTEXT | PM_WKUPAON_TIMER12_WKDEP[9]WKUPDEP_TIMER12_EVE4 | RM_WKUPAON_SAR_RAM_CONTEXT |
RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT | PM_WKUPAON_TIMER12_WKDEP[8]WKUPDEP_TIMER12_EVE3 | PM_WKUPAON_ADC_WKDEP |
RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT | PM_WKUPAON_TIMER12_WKDEP[7]WKUPDEP_TIMER12_EVE2 | RM_WKUPAON_ADC_CONTEXT |
PM_WKUPAON_WD_TIMER2_WKDEP[9]WKUPDEP_WD_TIMER2_EVE4 | PM_WKUPAON_TIMER12_WKDEP[6]WKUPDEP_TIMER12_EVE1 | PM_WKUPAON_KBD_WKDEP[8]WKUPDEP_KBD_EVE3 |
PM_WKUPAON_WD_TIMER2_WKDEP[8]WKUPDEP_WD_TIMER2_EVE3 | PM_WKUPAON_TIMER12_WKDEP[5]WKUPDEP_TIMER12_DSP2 | PM_WKUPAON_KBD_WKDEP[7]WKUPDEP_KBD_EVE2 |
PM_WKUPAON_WD_TIMER2_WKDEP[7]WKUPDEP_WD_TIMER2_EVE2 | PM_WKUPAON_KBD_WKDEP[9]WKUPDEP_KBD_EVE4 | PM_WKUPAON_KBD_WKDEP[6]WKUPDEP_KBD_EVE1 |
PM_WKUPAON_WD_TIMER2_WKDEP[6]WKUPDEP_WD_TIMER2_EVE1 | CM_L4PER3_TIMER13_CLKCTRL[27:24]CLKSEL=0x9 | PM_WKUPAON_KBD_WKDEP[5]WKUPDEP_KBD_DSP2 |
PM_WKUPAON_WD_TIMER2_WKDEP[5]WKUPDEP_WD_TIMER2_DSP2 | CM_L4PER3_TIMER14_CLKCTRL[27:24]CLKSEL=0x9 | PM_WKUPAON_UART10_WKDEP[9]WKUPDEP_UART10_EVE4 |
PM_WKUPAON_GPIO1_WKDEP[19]WKUPDEP_GPIO1_IRQ2_EVE4 | CM_L4PER3_TIMER15_CLKCTRL[27:24]CLKSEL=0x9 | PM_WKUPAON_UART10_WKDEP[8]WKUPDEP_UART10_EVE3 |
PM_WKUPAON_GPIO1_WKDEP[18]WKUPDEP_GPIO1_IRQ2_EVE3 | CM_L4PER3_TIMER16_CLKCTRL[27:24]CLKSEL=0x9 | PM_WKUPAON_UART10_WKDEP[7]WKUPDEP_UART10_EVE2 |
PM_WKUPAON_GPIO1_WKDEP[17]WKUPDEP_GPIO1_IRQ2_EVE2 | CM_IPU_MCASP1_CLKCTRL[23:22]CLKSEL_AUX_CLK=0x2 | PM_WKUPAON_UART10_WKDEP[6]WKUPDEP_UART10_EVE1 |
PM_WKUPAON_GPIO1_WKDEP[16]WKUPDEP_GPIO1_IRQ2_EVE1 | CM_ATL_ATL_CLKCTRL[25:24]CLKSEL_SOURCE1=0x2 | PM_WKUPAON_UART10_WKDEP[5]WKUPDEP_UART10_DSP2 |
PM_WKUPAON_GPIO1_WKDEP[15]WKUPDEP_GPIO1_IRQ2_DSP2 | CM_DSS_CLKSTCTRL[12]CLKACTIVITY_VIDEO2_DPLL_CLK | PM_WKUPAON_DCAN1_WKDEP[9]WKUPDEP_DCAN1_EVE4 |
CM_L4PER_TIMER4_CLKCTRL[27:24]CLKSEL=0x9 | CM_DSS_DSS_CLKCTRL[13]OPTFCLKEN_VIDEO2_CLK | PM_WKUPAON_DCAN1_WKDEP[8]WKUPDEP_DCAN1_EVE3 |
CM_IPU_TIMER5_CLKCTRL[27:24]CLKSEL=0x9 | CM_GMAC_GMAC_CLKCTRL[27:25]CLKSEL_RFT=0x1 | PM_WKUPAON_DCAN1_WKDEP[7]WKUPDEP_DCAN1_EVE2 |
CM_IPU_TIMER6_CLKCTRL[27:24]CLKSEL=0x9 | CM_CLKSEL_CLKOUT1[4:0]CLKSEL=0x15 | PM_WKUPAON_DCAN1_WKDEP[6]WKUPDEP_DCAN1_EVE1 |
CM_IPU_TIMER7_CLKCTRL[27:24]CLKSEL=0x9 | CM_L4PER2_CLKSTCTRL[13]CLKACTIVITY_PER_192M_GFCLK | PM_WKUPAON_DCAN1_WKDEP[5]WKUPDEP_DCAN1_DSP2 |
CM_IPU_TIMER8_CLKCTRL[27:24]CLKSEL=0x9 | CM_DIV_M3_DPLL_CORE | CM_L4PER_TIMER2_CLKCTRL[27:24]CLKSEL=0x9 |
CM_L4PER_TIMER9_CLKCTRL[27:24]CLKSEL=0x9 | CM_SSC_MODFREQDIV_DPLL_EVE | CM_L4PER_TIMER3_CLKCTRL[27:24]CLKSEL=0x9 |
CM_L4PER_TIMER10_CLKCTRL[27:24]CLKSEL=0x9 | CM_BYPCLK_DPLL_EVE | CM_L4PER2_MCASP2_CLKCTRL[23:22]CLKSEL_AUX_CLK=0x2 |
CM_L4PER_TIMER11_CLKCTRL[27:24]CLKSEL=0x9 | CM_DIV_H14_DPLL_GMAC | CM_L4PER2_MCASP3_CLKCTRL[23:22]CLKSEL_AUX_CLK=0x2 |
CM_CLKSEL_CLKOUT3[4:0]CLKSEL=0xA | CM_SSC_DELTAMSTEP_DPLL_GMAC | CM_L4PER2_MCASP5_CLKCTRL[23:22]CLKSEL_AUX_CLK=0x2 |
CM_CLKSEL_CLKOUT3[4:0]CLKSEL=0x15 | CM_SSC_MODFREQDIV_DPLL_GMAC | CM_L4PER2_MCASP8_CLKCTRL[23:22]CLKSEL_AUX_CLK=0x2 |
CM_L4PER2_CLKSTCTRL[8] CLKACTIVITY_ICSS_CLK | CM_DIV_M3_DPLL_GPU | CM_L4PER2_MCASP4_CLKCTRL[23:22]CLKSEL_AUX_CLK=0x2 |
CM_SSC_DELTAMSTEP_DPLL_CORE | CM_SSC_DELTAMSTEP_DPLL_GPU | CM_L4PER2_MCASP6_CLKCTRL[23:22]CLKSEL_AUX_CLK=0x2 |
CM_SSC_MODFREQDIV_DPLL_CORE | CM_SSC_MODFREQDIV_DPLL_GPU | CM_L4PER2_MCASP7_CLKCTRL[23:22]CLKSEL_AUX_CLK=0x2 |
CM_DIV_H21_DPLL_CORE | CM_DIV_M3_DPLL_PER | CM_CLKSEL_CLKOUT1[4:0]CLKSEL=0xA |
CM_SSC_DELTAMSTEP_DPLL_MPU | CM_SSC_DELTAMSTEP_DPLL_PER | CM_CLKSEL_CLKOUT2[4:0]CLKSEL=0xA |
CM_SSC_MODFREQDIV_DPLL_MPU | CM_SSC_MODFREQDIV_DPLL_PER | CM_CLKSEL_CLKOUT2[4:0]CLKSEL=0x15 |
CM_DIV_M3_DPLL_IVA | CM_SSC_DELTAMSTEP_DPLL_USB | CM_L4PER2_CLKSTCTRL[14] CLKACTIVITY_ICSS_IEP_CLK |
CM_SSC_DELTAMSTEP_DPLL_IVA | CM_SSC_MODFREQDIV_DPLL_USB | CM_DIV_H11_DPLL_CORE |
CM_SSC_MODFREQDIV_DPLL_IVA | CM_SSC_DELTAMSTEP_DPLL_PCIE_REF | CM_L3MAIN1_OCMC_RAM3_CLKCTRL |
CM_SSC_DELTAMSTEP_DPLL_ABE | CM_SSC_MODFREQDIV_DPLL_PCIE_REF | CM_L3MAIN1_OCMC_ROM_CLKCTRL |
CM_SSC_MODFREQDIV_DPLL_ABE | CM_COREAON_SMARTREFLEX_MPU_CLKCTRL | CM_L3MAIN1_SPARE_CME_CLKCTRL |
CM_DIV_M3_DPLL_DDR | CM_COREAON_SMARTREFLEX_CORE_CLKCTRL | CM_L3MAIN1_SPARE_HDMI_CLKCTRL |
CM_SSC_DELTAMSTEP_DPLL_DDR | CM_COREAON_IO_SRCOMP_CLKCTRL | CM_L3MAIN1_SPARE_ICM_CLKCTRL |
CM_SSC_MODFREQDIV_DPLL_DDR | CM_COREAON_SMARTREFLEX_GPU_CLKCTRL | CM_L3MAIN1_SPARE_IVA2_CLKCTRL |
CM_SSC_MODFREQDIV_DPLL_DSP | CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL | CM_L3MAIN1_SPARE_SATA2_CLKCTRL |
CM_RESTORE_ST | CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL | CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL |
CM_CLKMODE_DPLL_EVE | CM_L3MAIN1_OCMC_RAM2_CLKCTRL | CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL |
CM_IDLEST_DPLL_EVE | PM_L3MAIN1_TPTC1_WKDEP[9]WKUPDEP_TPTC1_EVE4 | CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL |
CM_AUTOIDLE_DPLL_EVE | PM_L3MAIN1_TPTC1_WKDEP[8]WKUPDEP_TPTC1_EVE3 | CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL |
CM_CLKSEL_DPLL_EVE | PM_L3MAIN1_TPTC1_WKDEP[7]WKUPDEP_TPTC1_EVE2 | CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL |
CM_DIV_M2_DPLL_EVE | PM_L3MAIN1_TPTC1_WKDEP[6]WKUPDEP_TPTC1_EVE1 | CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL |
CM_DIV_M3_DPLL_EVE | PM_L3MAIN1_TPTC1_WKDEP[5]WKUPDEP_TPTC1_DSP2 | CM_EMIF_EMIF2_CLKCTRL |
CM_SSC_DELTAMSTEP_DPLL_EVE | CM_CLKMODE_DPLL_DDR[15]DPLL_SSC_TYPE | CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL |
CM_CLKMODE_DPLL_IVA[15]DPLL_SSC_TYPE | CM_CLKMODE_DPLL_DDR[14]DPLL_SSC_DOWNSPREAD | CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL |
CM_CLKMODE_DPLL_IVA[14]DPLL_SSC_DOWNSPREAD | CM_CLKMODE_DPLL_DDR[13]DPLL_SSC_ACK | CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL |
CM_CLKMODE_DPLL_IVA[13]DPLL_SSC_ACK | CM_CLKMODE_DPLL_DDR[12]DPLL_SSC_EN | CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL |
CM_CLKMODE_DPLL_IVA[12]DPLL_SSC_EN | CM_CLKMODE_DPLL_DSP[15]DPLL_SSC_TYPE | CM_DSS_SDVENC_CLKCTRL |
CM_L4PER2_STATICDEP[18]DSP2_STATDEP | CM_CLKMODE_DPLL_DSP[14]DPLL_SSC_DOWNSPREAD | CM_L3INIT_USB_OTG_SS4_CLKCTRL |
CM_COREAON_CLKSTCTRL[14]CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK | CM_CLKMODE_DPLL_DSP[13]DPLL_SSC_ACK | CM_COREAON_IO_SRCOMP_CLKCTRL_RESTORE |
CM_L3MAIN1_DYNAMICDEP[31]EVE4_DYNDEP | CM_CLKMODE_DPLL_DSP[12]DPLL_SSC_EN | CM_PCIE_STATICDEP[19]EVE1_STATDEP |
CM_L3MAIN1_DYNAMICDEP[30]EVE3_DYNDEP | CM_PCIE_STATICDEP[22]EVE4_STATDEP | CM_PCIE_STATICDEP[18]DSP2_STATDEP |
CM_L3MAIN1_DYNAMICDEP[29]EVE2_DYNDEP | CM_PCIE_STATICDEP[21]EVE3_STATDEP | CM_CLKMODE_DPLL_MPU[15]DPLL_SSC_TYPE |
CM_L3MAIN1_DYNAMICDEP[28]EVE1_DYNDEP | CM_PCIE_STATICDEP[20]EVE2_STATDEP | CM_CLKMODE_DPLL_MPU[14]DPLL_SSC_DOWNSPREAD |
CM_L3MAIN1_DYNAMICDEP[20]DSP2_DYNDEP | CM_DSS_CLKSTCTRL[16]CLKACTIVITY_DSS_SYS_GFCLK | CM_CLKMODE_DPLL_MPU[13]DPLL_SSC_ACK |
CM_L3INIT_CLKSTCTRL[14]CLKACTIVITY_HSI_GFCLK | CM_DSS_CLKSTCTRL[14]CLKACTIVITY_SDVENC_GFCLK | CM_CLKMODE_DPLL_MPU[12]DPLL_SSC_EN |
CM_CLKMODE_DPLL_GPU[15]DPLL_SSC_TYPE | CM_CLKMODE_DPLL_USB[15]DPLL_SSC_TYPE | CM_CLKMODE_DPLL_GMAC[15]DPLL_SSC_TYPE |
CM_CLKMODE_DPLL_GPU[14]DPLL_SSC_DOWNSPREAD | CM_CLKMODE_DPLL_USB[14]DPLL_SSC_DOWNSPREAD | CM_CLKMODE_DPLL_GMAC[14]DPLL_SSC_DOWNSPREAD |
CM_CLKMODE_DPLL_GPU[13]DPLL_SSC_ACK | CM_CLKMODE_DPLL_USB[13]DPLL_SSC_ACK | CM_CLKMODE_DPLL_GMAC[13]DPLL_SSC_ACK |
CM_CLKMODE_DPLL_GPU[12]DPLL_SSC_EN | CM_CLKMODE_DPLL_USB[12]DPLL_SSC_EN | CM_CLKMODE_DPLL_GMAC[12]DPLL_SSC_EN |
CM_DSP1_STATICDEP[22]EVE4_STATDEP | CM_CLKMODE_DPLL_CORE[15]DPLL_SSC_TYPE | CM_IPU2_STATICDEP[22]EVE4_STATDEP |
CM_DSP1_STATICDEP[21]EVE3_STATDEP | CM_CLKMODE_DPLL_CORE[14]DPLL_SSC_DOWNSPREAD | CM_IPU2_STATICDEP[21]EVE3_STATDEP |
CM_DSP1_STATICDEP[20]EVE2_STATDEP | CM_CLKMODE_DPLL_CORE[13]DPLL_SSC_ACK | CM_IPU2_STATICDEP[20]EVE2_STATDEP |
CM_DSP1_STATICDEP[19]EVE1_STATDEP | CM_CLKMODE_DPLL_CORE[12]DPLL_SSC_EN | CM_IPU2_STATICDEP[19]EVE1_STATDEP |
CM_DSP1_STATICDEP[18]DSP2_STATDEP | CM_IPU1_STATICDEP[22]EVE4_STATDEP | CM_IPU2_STATICDEP[18]DSP2_STATDEP |
CM_CLKMODE_DPLL_PCIE_REF[13]DPLL_SSC_ACK | CM_IPU1_STATICDEP[21]EVE3_STATDEP | CM_CLKMODE_DPLL_ABE[15]DPLL_SSC_TYPE |
CM_CLKMODE_DPLL_PCIE_REF[12]DPLL_SSC_EN | CM_IPU1_STATICDEP[20]EVE2_STATDEP | CM_CLKMODE_DPLL_ABE[14]DPLL_SSC_DOWNSPREAD |
CM_EMIF_EMIF1_CLKCTRL[24]CLKSEL_LL | CM_IPU1_STATICDEP[19]EVE1_STATDEP | CM_CLKMODE_DPLL_ABE[13]DPLL_SSC_ACK |
CM_MPU_STATICDEP[22]EVE4_STATDEP | CM_IPU1_STATICDEP[18]DSP2_STATDEP | CM_CLKMODE_DPLL_ABE[12]DPLL_SSC_EN |
CM_MPU_STATICDEP[21]EVE3_STATDEP | CM_CLKSEL_ABE[10]SLIMBUS1_CLK_GATE | CM_CLKMODE_DPLL_PER[15]DPLL_SSC_TYPE |
CM_MPU_STATICDEP[20]EVE2_STATDEP | PM_L3MAIN1_TPTC2_WKDEP[5]WKUPDEP_TPTC2_DSP2 | CM_CLKMODE_DPLL_PER[14]DPLL_SSC_DOWNSPREAD |
CM_MPU_STATICDEP[19]EVE1_STATDEP | CM_CLKMODE_DPLL_PCIE_REF[15]DPLL_SSC_TYPE | CM_CLKMODE_DPLL_PER[13]DPLL_SSC_ACK |
CM_MPU_STATICDEP[18]DSP2_STATDEP | CM_CLKMODE_DPLL_PCIE_REF[14]DPLL_SSC_DOWNSPREAD | CM_CLKMODE_DPLL_PER[12]DPLL_SSC_EN |
PM_L3MAIN1_TPTC2_WKDEP[9]WKUPDEP_TPTC2_EVE4 | CM_SSC_DELTAMSTEP_DPLL_DSP | CM_L4PER_CLKSTCTRL[25]CLKACTIVITY_PER_192M_GFCLK |
PM_L3MAIN1_TPTC2_WKDEP[8]WKUPDEP_TPTC2_EVE3 | PM_L3MAIN1_TPTC2_WKDEP[7]WKUPDEP_TPTC2_EVE2 | PM_L3MAIN1_TPTC2_WKDEP[6]WKUPDEP_TPTC2_EVE1 |
CM_CLKSEL_SYS[2:0]SYS_CLKSEL=0x5 | CM_CLKSEL_SYS[2:0]SYS_CLKSEL=0x1 | CM_CLKSEL_SYS[2:0]SYS_CLKSEL=0x3 |
CM_COREAON_CLKSTCTRL[13]CLKACTIVITY_SR_DSPEVE_SYS_GFCLK | CM_CLKSEL_SYS[2:0]SYS_CLKSEL=0x7 | CM_COREAON_CLKSTCTRL[15]CLKACTIVITY_SR_IVAHD_SYS_GFCLK |
CM_COREAON_CLKSTCTRL[11]CLKACTIVITY_SR_CORE_SYS_GFCLK | CM_COREAON_CLKSTCTRL[10]CLKACTIVITY_SR_GPU_SYS_GFCLK | CM_COREAON_CLKSTCTRL[8]CLKACTIVITY_COREAON_L4_GICLK |
CM_COREAON_CLKSTCTRL[9]CLKACTIVITY_SR_MPU_SYS_GFCLK | RM_L3MAIN1_L3_MAIN_1_CONTEXT | RM_L4CFG_MAILBOX7_CONTEXT |
RM_IPU_MCASP1_CONTEXT | RM_L3MAIN1_GPMC_CONTEXT | RM_L4CFG_MAILBOX8_CONTEXT |
RM_IPU_TIMER5_CONTEXT | RM_L3MAIN1_MMU_EDMA_CONTEXT | RM_L4CFG_MAILBOX9_CONTEXT |
RM_IPU_TIMER6_CONTEXT | RM_L3MAIN1_MMU_PCIESS_CONTEXT | RM_L4CFG_MAILBOX10_CONTEXT |
RM_IPU_TIMER7_CONTEXT | RM_L3MAIN1_OCMC_RAM1_CONTEXT | RM_L4CFG_MAILBOX11_CONTEXT |
RM_IPU_TIMER8_CONTEXT | RM_L3MAIN1_TPCC_CONTEXT | RM_L4CFG_MAILBOX12_CONTEXT |
RM_IPU_I2C5_CONTEXT | RM_L3MAIN1_TPTC1_CONTEXT | RM_L4CFG_MAILBOX13_CONTEXT |
RM_IPU_UART6_CONTEXT | RM_L3MAIN1_TPTC2_CONTEXT | RM_L3INSTR_L3_MAIN_2_CONTEXT |
RM_L3INIT_MMC1_CONTEXT | RM_L3MAIN1_VCP1_CONTEXT | RM_L3INSTR_L3_INSTR_CONTEXT |
RM_L3INIT_MMC2_CONTEXT | RM_L3MAIN1_VCP2_CONTEXT | RM_L3INSTR_OCP_WP_NOC_CONTEXT |
RM_L3INIT_MLB_SS_CONTEXT | RM_DMA_DMA_SYSTEM_CONTEXT | PM_L4PER_PWRSTST |
RM_L3INIT_IEEE1500_2_OCP_CONTEXT | RM_EMIF_DMM_CONTEXT | PM_L4PER_PWRSTCTRL |
RM_GMAC_GMAC_CONTEXT | RM_EMIF_EMIF_OCP_FW_CONTEXT | RM_L4PER2_L4PER2_CONTEXT |
RM_L3INIT_OCP2SCP1_CONTEXT | RM_EMIF_EMIF1_CONTEXT | RM_L4PER3_L4PER3_CONTEXT |
RM_L3INIT_OCP2SCP3_CONTEXT | RM_EMIF_EMIF_DLL_CONTEXT | RM_L4PER2_PRUSS1_CONTEXT |
PM_L3INIT_PWRSTCTRL[10]GMAC_BANK_RETSTATE | RM_ATL_ATL_CONTEXT | RM_L4PER2_PRUSS2_CONTEXT |
PM_L3INIT_PWRSTCTRL[19:18]GMAC_BANK_ONSTATE | RM_L4CFG_L4_CFG_CONTEXT | RM_L4PER_TIMER10_CONTEXT |
PM_L3INIT_PWRSTST[9:8]L3INIT_GMAC_STATEST | RM_L4CFG_SPINLOCK_CONTEXT | RM_L4PER_TIMER11_CONTEXT |
PM_CORE_PWRSTCTRL[25:24]OCP_NRET_BANK_ONSTATE | RM_L4CFG_MAILBOX1_CONTEXT | RM_L4PER_TIMER2_CONTEXT |
PM_CORE_PWRSTCTRL[19:18]CORE_OCMRAM_ONSTATE | RM_L4CFG_SAR_ROM_CONTEXT | RM_L4PER_TIMER3_CONTEXT |
PM_CORE_PWRSTCTRL[17:16]CORE_OTHER_BANK_ONSTATE | RM_L4CFG_MAILBOX2_CONTEXT | RM_L4PER_TIMER4_CONTEXT |
PM_CORE_PWRSTCTRL[12]OCP_NRET_BANK_RETSTATE | RM_L4CFG_OCP2SCP2_CONTEXT | RM_L4PER_TIMER9_CONTEXT |
PM_CORE_PWRSTCTRL[9]CORE_OCMRAM_RETSTATE | RM_L4CFG_MAILBOX3_CONTEXT | RM_L4PER_ELM_CONTEXT |
PM_CORE_PWRSTCTRL[8]CORE_OTHER_BANK _RETSTATE | RM_L4CFG_MAILBOX4_CONTEXT | RM_L4PER_GPIO2_CONTEXT |
PM_CORE_PWRSTST[13:12]OCP_NRET_BANK_STATEST | RM_L4CFG_MAILBOX5_CONTEXT | RM_L4PER_GPIO3_CONTEXT |
PM_CORE_PWRSTST[7:6]CORE_OCMRAM_STATEST | RM_L4CFG_MAILBOX6_CONTEXT | RM_L4PER_GPIO4_CONTEXT |
PM_CORE_PWRSTST[5:4]CORE_OTHER_BANK_STATEST | RM_L4PER3_TIMER13_CONTEXT | RM_L4PER_GPIO6_CONTEXT |
RM_L4PER_HDQ1W_CONTEXT | RM_L4PER3_TIMER14_CONTEXT | RM_L4PER_MMC3_CONTEXT |
RM_L4PER2_PWMSS2_CONTEXT | RM_L4PER3_TIMER15_CONTEXT | RM_L4PER_MMC4_CONTEXT |
RM_L4PER2_PWMSS3_CONTEXT | RM_L4PER_MCSPI1_CONTEXT | RM_L4PER3_TIMER16_CONTEXT |
RM_L4PER_I2C1_CONTEXT | RM_L4PER_MCSPI2_CONTEXT | RM_L4PER2_QSPI_CONTEXT |
RM_L4PER_I2C2_CONTEXT | RM_L4PER_MCSPI3_CONTEXT | RM_L4PER_UART1_CONTEXT |
RM_L4PER_I2C3_CONTEXT | RM_L4PER_MCSPI4_CONTEXT | RM_L4PER_UART2_CONTEXT |
RM_L4PER_I2C4_CONTEXT | RM_L4PER_GPIO7_CONTEXT | RM_L4PER_UART3_CONTEXT |
RM_L4PER_L4PER1_CONTEXT | RM_L4PER_GPIO8_CONTEXT | RM_L4PER_UART4_CONTEXT |
RM_L4PER2_PWMSS1_CONTEXT | RM_L4PER2_MCASP6_CONTEXT | RM_L4PER2_MCASP2_CONTEXT |
RM_L4PER2_MCASP3_CONTEXT | RM_L4PER2_MCASP7_CONTEXT | RM_L4PER2_MCASP4_CONTEXT |
RM_L4PER_UART5_CONTEXT | RM_L4PER2_MCASP8_CONTEXT | RM_L4SEC_AES1_CONTEXT |
RM_L4PER2_MCASP5_CONTEXT | RM_L4PER2_UART7_CONTEXT | RM_L4SEC_AES2_CONTEXT |
RM_L4SEC_DES3DES_CONTEXT | RM_L4SEC_DMA_CRYPTO_CONTEXT | RM_L4PER2_DCAN2_CONTEXT |
RM_L4SEC_FPKA_CONTEXT | RM_L4PER2_UART8_CONTEXT | RM_L4SEC_SHA2MD52_CONTEXT |
RM_L4SEC_RNG_CONTEXT | RM_L4PER2_UART9_CONTEXT | PM_EMU_PWRSTCTRL |
RM_L4SEC_SHA2MD51_CONTEXT | RM_L4PER_GPIO5_CONTEXT | PM_EMU_PWRSTST |
RM_EMU_DEBUGSS_CONTEXT | CM_L4CFG_SAR_ROM_CLKCTRL | PRM_PHASE1_CNDP |
PRM_PHASE2A_CNDP | PRM_PHASE2B_CNDP | CM_CAM_CAL_CLKCTRL[18]STBYST |
CM_CAM_LVDSRX_CLKCTRL | RM_CAM_LVDSRX_CONTEXT | PM_DSP1_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x1 |
PM_IVA_PWRSTCTRL[11] TCM2_MEM_RETSTATE | PM_CORE_PWRSTCTRL [1:0] POWERSTATE =0x1 | PM_DSP1_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x2 |
PM_IVA_PWRSTCTRL[10] TCM1_MEM_RETSTATE | PM_CORE_PWRSTCTRL [1:0] POWERSTATE =0x2 | PM_IPU_PWRSTCTRL [1:0] POWERSTATE =0x1 |
PM_IVA_PWRSTCTRL[9] SL2_MEM_RETSTATE | PM_CORE_PWRSTCTRL [2] LOGICRETSTATE | PM_IPU_PWRSTCTRL [1:0] POWERSTATE =0x2 |
PM_IVA_PWRSTCTRL[8] HWA_MEM_RETSTATE | PM_CORE_PWRSTCTRL [10] IPU_L2RAM_RETSTATE | PM_IPU_PWRSTCTRL [2] LOGICRETSTATE |
PM_IVA_PWRSTCTRL[2] LOGICRETSTATE | PM_CORE_PWRSTCTRL [11] IPU_UNICACHE_RETSTATE | PM_IPU_PWRSTCTRL [8] AESSMEM_RETSTATE |
PM_IVA_PWRSTCTRL[1:0] POWERSTATE =0x2 | PM_CORE_PWRSTST [1:0] POWERSTATEST=0x1 | PM_IPU_PWRSTCTRL [10] PERIPHMEM_RETSTATE |
PM_IVA_PWRSTCTRL[1:0] POWERSTATE =0x1 | PM_CORE_PWRSTST [1:0] POWERSTATEST=0x2 | PM_IPU_PWRSTST [1:0] POWERSTATEST =0x1 |
PM_IVA_PWRSTST[25:24] LASTPOWERSTATEENTERED =0x1 | PM_CORE_PWRSTST [9:8] IPU_L2RAM_STATEST =0x1 | PM_IPU_PWRSTST [1:0] POWERSTATEST =0x2 |
PM_IVA_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x2 | PM_CORE_PWRSTST [11:10] IPU_UNICACHE_STATEST =0x1 | PM_IPU_PWRSTST [5:4] AESSMEM_STATEST =0x1 |
PM_IVA_PWRSTST [11:10] TCM2_MEM_STATEST =0x1 | PM_CORE_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x1 | PM_IPU_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x1 |
PM_IVA_PWRSTST [9:8] TCM1_MEM_STATEST =0x1 | PM_CORE_PWRSTST [25:24] LASTPOWERSTATEENTERED=0x2 | PM_IPU_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x2 |
PM_IVA_PWRSTST [7:6] SL2_MEM_STATEST =0x1 | PM_VPE_PWRSTCTRL [1:0] POWERSTATE =0x1 | PM_L3INIT_PWRSTST[25:24] LASTPOWERSTATEENTERED=0x1 |
PM_IVA_PWRSTST [5:4] HWA_MEM_STATEST=0x1 | PM_VPE_PWRSTCTRL [1:0] POWERSTATE =0x2 | PM_L3INIT_PWRSTST[25:24] LASTPOWERSTATEENTERED=0x2 |
PM_IVA_PWRSTST [1:0] POWERSTATEST =0x1 | PM_VPE_PWRSTCTRL [2] LOGICRETSTATE | PM_L3INIT_PWRSTST[7:6] L3INIT_BANK2_STATEST=0x1 |
PM_IVA_PWRSTST [1:0] POWERSTATEST =0x2 | PM_VPE_PWRSTCTRL [8] VPE_BANK_RETSTATE | PM_L3INIT_PWRSTST[1:0] POWERSTATEST=0x1 |
PM_CUSTEFUSE_PWRSTCTRL [1:0] POWERSTATE =0x2 | PM_VPE_PWRSTST [1:0] POWERSTATEST =0x1 | PM_L3INIT_PWRSTST[1:0] POWERSTATEST=0x2 |
PM_CUSTEFUSE_PWRSTST [1:0] POWERSTATEST =0x1 | PM_VPE_PWRSTST [1:0] POWERSTATEST =0x2 | PM_IVA_PWRSTST[2]LOGICSTATEST=0x0 |
PM_CUSTEFUSE_PWRSTST [1:0] POWERSTATEST =0x2 | PM_VPE_PWRSTST [5:4] VPE_BANK_STATEST =0x1 | PM_CUSTEFUSE_PWRSTST[2]LOGICSTATEST=0x0 |
PM_CUSTEFUSE_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x1 | PM_VPE_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x1 | PM_DSS_PWRSTST[2]LOGICSTATEST=0x0 |
PM_CUSTEFUSE_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x2 | PM_VPE_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x2 | PM_GPU_PWRSTST[2]LOGICSTATEST=0x0 |
PM_DSS_PWRSTCTRL [8] DSS_MEM_RETSTATE | PM_CAM_PWRSTCTRL [1:0] POWERSTATE =0x2 | PM_CORE_PWRSTST[2]LOGICSTATEST=0x0 |
PM_DSS_PWRSTCTRL [2] LOGICRETSTATE | PM_CAM_PWRSTST [1:0] POWERSTATEST =0x1 | PM_VPE_PWRSTST[2]LOGICSTATEST=0x0 |
PM_DSS_PWRSTCTRL [1:0] POWERSTATE =0x1 | PM_CAM_PWRSTST [1:0] POWERSTATEST =0x2 | PM_CAM_PWRSTST[2]LOGICSTATEST=0x0 |
PM_DSS_PWRSTCTRL [1:0] POWERSTATE =0x2 | PM_CAM_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x1 | PM_L3INIT_PWRSTST[2]LOGICSTATEST=0x0 |
PM_DSS_PWRSTST [1:0] POWERSTATEST =0x1 | PM_CAM_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x2 | PM_DSP1_PWRSTST[2]LOGICSTATEST=0x0 |
PM_DSS_PWRSTST [1:0] POWERSTATEST =0x2 | PM_L3INIT_PWRSTCTRL [1:0] POWERSTATE =0x1 | PM_IPU_PWRSTST[2]LOGICSTATEST=0x0 |
PM_DSS_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x1 | PM_L3INIT_PWRSTCTRL [1:0] POWERSTATE =0x2 | PRM_IRQENABLE_DSP1[13]DPLL_USB_RECAL_EN |
PM_DSS_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x2 | PM_L3INIT_PWRSTCTRL [2] LOGICRETSTATE | |
PM_GPU_PWRSTCTRL [1:0] POWERSTATE =0x2 | PM_L3INIT_PWRSTCTRL [8] L3INIT_BANK1_RETSTATE | |
PM_GPU_PWRSTST [1:0] POWERSTATEST =0x1 | PM_L3INIT_PWRSTCTRL [9] L3INIT_BANK2_RETSTATE | |
PM_GPU_PWRSTST [1:0] POWERSTATEST =0x2 | PM_DSP1_PWRSTCTRL [1:0] POWERSTATE =0x2 | |
PM_GPU_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x1 | PM_DSP1_PWRSTST [1:0] POWERSTATEST =0x1 | |
PM_GPU_PWRSTST [25:24] LASTPOWERSTATEENTERED =0x2 | PM_DSP1_PWRSTST [1:0] POWERSTATEST =0x2 |