SWRU455M February 2017 – October 2020 CC3120 , CC3120MOD , CC3130 , CC3135 , CC3135MOD , CC3220MOD , CC3220MODA , CC3220R , CC3220S , CC3220SF , CC3230S , CC3230SF , CC3235MODAS , CC3235MODASF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF
The CC31XX may share the SPI bus with other slaves, all connected to a single master. In this case, the CLK, MOSI, and MISO lines are shared with the other slaves, and the CC31XX has its own CSn to signal which messages are directed to the CC31XX. The MISO line goes into HiZ state between words the CC31XX is transmitting, to avoid possible contention with the other slaves.
Figure 25-4 shows a typical multi-slave configuration.
The other slaves must also have their MISO lines tri-stated between data writing cycles to prevent the risk of line contention or data corruption.
When a single SPI slave configuration is used (not shared SPI mode) and in the case of a pin limited platform, the user may want to eliminate the CS line and tie it to GND. This option is NOT supported by the current CC3100 revision.
Table 25-2 summarizes the different supported configurations.
Property | Supported CC3100 Configuration |
---|---|
Clock polarity | Data is output on the clock’s falling edge, sampled on the rising edge |
Clock phase | Clock idles at logical 0 |
Word size | 32/16/8 bits |
Host Endianity | Little Endian / Big Endian |
Bit order | MSBit first |
Chip select polarity | Active low |
Host Interrupt polarity | Active high |
Host Interrupt mode | Rising edge or level ‘1’ |
Clock Frequency | Up to 20MHz |
Chip select assertion between words | Optional (CSn can be kept asserted for entire message) |
3-Wires mode | Not supported |
Shared SPI | Supported |
The host Endianity and word size are automatically detected by the SimpleLink™ device with no special configuration or handling in the host application.
For exact timing requirements, refer to the CC31XX data sheet.