Calculating Useful Lifetimes of Embedded Processors
Calculating Useful Lifetimes of Embedded Processors
This application report provides a methodology for calculating the useful lifetime of TI embedded processors (EP) under power when used in electronic systems. It is aimed at general engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement. Electro-migration is the primary failure mechanism being modeled.
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1 Introduction
This document introduces the three stages of reliability and shows the current generation of TI industrial grade EP product is designed to support a useful lifetime of 10 year operating at 105°C junction temperature (TJ).
Based on the physics of failure approach, it shows useful life scales with temperature and decreasing the effective temperature below 105°C TJ, can extend the useful lifetime of the silicon beyond 10 years. Similarly, increasing the effective temperature above the 105°C TJ will shorten lifetime.
Using a case study of an actual system level mission profile, it shows how to calculate if the EP will be operating within its target useful lifetime for which it was designed.
2 Stages of Reliability and Useful Life Period
When considering ‘reliability’, three phases of lifetimes are considered:
- Early life – declining failure rate where failures are due to random defects.
- Useful life – the steady state period where failure rate is relatively constant.
- Wear-out – stage where end of life mechanisms start to occur and failure rate increases.
Figure 1 illustrates this as a “bathtub curve” profile where the edges of the curves reflect the shape of a bath.
The focus of electronics reliability is the useful life period and also referred to as steady-state period where it is expressed in Failure in Time (FIT): # of failures/109 hours.
Figure 1. Bathtub Curve Showing Different Stages of Reliability Many industrial systems require useful lifetimes of 10 years or less but recent examples of reliability profiles modeled by TI that go above that include:
- Telecommunication equipment: 15 years continuous operation
- Industrial controllers in factory electrical supply system: 15 years continuous operation
- Solar invertor: 15 years continuous operation
- Water meter: 15 years continuous operation
- Electronic Meter: 20 years continuous operation
3 CMOS Wear Out Mechanisms and IC Design
The current generation of TI industrial grade embedded processor products is designed to support a useful lifetime of 10 year operating at 105°C junction temperature TJ.
The 10 year lifetime assumes a worst case situation of 100% powered on and run at a constant 105°C TJ temperature.
TI EP products are designed for reliability so that the onset of the wear out mechanisms occurs beyond the useful life period. This is illustrated in Figure 1.
Robustness to prominent silicon wear-out mechanisms that are designed for include:
- Gate oxide integrity (GOI)
- Electro-migration (EM)
- Time dependent di-electric breakdown (TDDB)
In addition, mechanisms that cause parametric shift over lifetime, such as Negative Bias Temperature Instability (NBTI) and Channel Hot Carriers (CHC), are also considered within the product design.
For most silicon technologies, the critical wear out mechanism is EM.
