SPRACN9F May 2023 – August 2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1
This application report contains material applicable to the LPDDR4 interface of Jacinto7 AM6x/TDA4x/DRA8x processor board designs.
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The Jacinto7 AM6x/TDA4x/DRA8x family of processors support LPDDR4 memory interfaces. This document contains specific information on how to design and implemented LPDDR4 memory interfaces with this family of devices.
To facilitate software configuration of the LPDDR4 subsystem, please refer the Jacinto7 DDRSS Register Configuration Tool (Link).