Dual-TDA4x System Solution

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1 Introduction

Jacinto TDA4x processors family is a scalable platform with software-compatible products. Based on systems requirements, TDA4x SoC family offers multiple products with different performance, power and feature-set that customers can choose from. Currently, the TDA4VM is production and details can be found at TDA4VM product page [1]. Table 1-1 shows a typical IP configuration of TDA4VM. For more information, see the DRA829/TDA4VM Technical Reference Manual [2].

Table 1-1 TDA4VM Typical Configuration

		Processor/Accelerator					Interface
TDA4VM	IP	Arm	Arm-R5F	DSP	GPU	MMA	DDR	Capture	PCIe	Ethernet
TDA4VM	Feature	2xA72 (~25K DMIPS)	3xDual R5F (3x ~12KDMIPS)	1xC7x+ 2xC66x	GE8430 (100 GFLOPs)	1xMMAv1 8TOPs	1x32b@4266Mhz	2x CSI-Rx (4L)	PCIe Gen3: 4x 2DL	8pswitch+ 1x RGMII (MCU)

Dual-TDA4x cascading solution may be required in below scenarios:

Performance Requirement
- Performance requirements for general processing, deep learning and customers applications running on MPU, might be too high for a single SoC.
Function Safety
- To meet functional safety requirements, a second TDA4x SoC might be required as a redundant SoCs as a backup system when main TDA4x device is abnormal.
Power and Thermal Consideration
- Dual SoC solution provides better power and thermal distribution where system load can be distributed across SoCs to enable better power and thermal management.
IO Interfaces
- In highly integrated system solutions, single SoC might not provide enough peripheral interfaces including camera , PCIe, Ethernet, CAN, LIN interfaces. Dual-SoC solution might be required to meet system interface requirements.

All the Jacinto TDA4VM SoCs are configured with Ethernet and PCIe interfaces. This means that all the TDA4x family processors can be interconnected via Ethernet and PCIe to enable dual-SoC system requirements. Next sections will discuss system considerations for such solution.

2 Dual TDA4 System

2.1 Dual TDA4x SoC System Diagram

An example highly integrated ADAS system based on dual TDA4VM SoCs is shown in Figure 1. This ADAS system integrates front-camera, 4 surround view cameras and 4 side view cameras on a single PCB and supports below main features:

Cameras are connected via MIPI CSI2-RX interface
- Each CSI2-RX port supports 4 lane and data rates up to 2.5Gbps per lane, totaling up to 10 Gbps per CSI2-RX port.
Each TDA4x SOC needs a dedicated power (PMIC) solution, however secondary TDA4x PMIC can be connected to primary TDA4x to achieve wake up function.
The front camera systems typically require high-resolution sensors to achieve complex functions such as object detection, parking assist and so on. In such scenario, multiple deep learning models need to work together. The original camera data can be duplicated to two TDA4x separately through de-serializers such as FPDLink.
The four side view cameras and four surround view cameras can be deployed on two TDA4x separately to balance functionality, processing load, power and thermal distribution.
Figure 2-1 Typical Dual TDA4 Cascading System Diagram
Two TDA4x SoCs can be connected via various high-speed interfaces including PCIe and Ethernet. The PCIe, Ethernet and SPI interconnection between the two TDA4x SoCs does not require the PHY chips, the pins can be directly connected through PCB. For example, the Ethernet switch (CPSW9G) interconnection between two TDA4x SoCs, or CPSW9G and CPSW2G interconnection in the same chip, are using MAC to MAC support without Ethernet PHY.
- The PCIe controller supports Gen3, 8 Gbps for each lane and up to 4 lanes per PCIe controller, providing total 32Gbps throughput.
- The 8-port Ethernet switch supports:
  - All ports support 2.5Gb HSGMII, 1GB SGMII/RGMII
  - Two ports supporting 5Gb/10Gb XFI/USXGMII
The external DDR memory and flash memories such as eMMC, OSPI/QSPI are required for each TDA4 to achieve the best performance. However, in some scenarios, further optimizations are possible to balance cost and system design.