SPRAD26 April 2022 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1
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SPI is a synchronous serial communication interface specification used for short-distance communication, primarily in embedded systems.
Salient features of SPI protocol are listed below:
The SPI bus specifies four logic signals:
MOSI on a master connects to MOSI on a slave. MISO on a master connects to MISO on a slave.
Slave Select has the same functionality as chip select and is used instead of an addressing concept.
MCSPI stands for Multichannel Serial Peripheral Interface (MCSPI). The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus. There are eleven MCSPI modules in the device (see Table 2-1).
Instance | Doman | ||
---|---|---|---|
WKUP | MCU | MAIN | |
MCU_MCSPI0 | - | ✓ | - |
MCU_MCSPI1 | - | ✓ | - |
MCU_MCSPI2 | - | ✓ | - |
MCSPI0 | - | - | ✓ |
MCSPI1 | - | - | ✓ |
MCSPI2 | - | - | ✓ |
MCSPI3 | - | - | ✓ |
MCSPI4 | - | - | ✓ |
MCSPI5 | - | - | ✓ |
MCSPI6 | - | - | ✓ |
MCSPI7 | v | - | ✓ |
For more information, see the J7200 DRA821 Processor Silicon Revision 1.0 Technical Reference Manual.
missing table
MCSPI4 is directly connected as a slave to MCU_MCSPI2 by default at power-up. MCSPI4 and
MCU_MCSPI2 are not pinned out externally.The MCSPI modules include the following main features:
For example lets us take main domain SPI6 instance. To enable SPI6, add the device tree node and the corresponding pinmux node.
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 6788a3611..77b845354 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -170,6 +170,18 @@
>;
};
+ spi6_pins_default: spi6_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x9c, PIN_INPUT, 4) /* (AC22) PRG1_PRU1_GPO17.SPI6_CLK */
+ J721E_IOPAD(0x74, PIN_INPUT, 4) /* (AC21) PRG1_PRU1_GPO7.SPI6_CS0 */
+ J721E_IOPAD(0x28, PIN_INPUT, 4) /* (AG20) PRG1_PRU0_GPO9.SPI6_CS1 */
+ J721E_IOPAD(0x2c, PIN_INPUT, 4) /* (AD21) PRG1_PRU0_GPO10.SPI6_CS2 */
+ J721E_IOPAD(0x7c, PIN_INPUT, 4) /* (AF21) PRG1_PRU1_GPO9.SPI6_CS3 */
+ J721E_IOPAD(0xa0, PIN_INPUT, 4) /* (AJ22) PRG1_PRU1_GPO18.SPI6_D0 */
+ J721E_IOPAD(0xa4, PIN_INPUT, 4) /* (AH22) PRG1_PRU1_GPO19.SPI6_D1 */
+ >;
+ };
+
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index c036df124..edc42720f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -74,6 +74,16 @@
};
};
+ main_spi6: spi@2160000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x2160000 0x0 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 272 1>;
+ power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
CONFIG_SPI_OMAP24XX=y is already set in arch/arm64/configs/tisdk_j7-evm_defconfig. The SPI master driver is drivers/spi/spi-omap2-mcspi.c.
Add a spidev node inside the spi6 node like below in arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts:
+&main_spi6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi6_pins_default>;
+ status="okay";
+
+ spidev@0 {
+
+ spi-max-frequency = <24000000>;
+ reg = <0>;
+ compatible = "linux,spidev";
+};
+};
Enable CONFIG_SPI_SPIDEV=y explicitly in arch/arm64/configs/tisdk_j7-evm_defconfig.
Once you boot Linux one should entries like below:
ls -l /sys/class/spi*
/sys/class/spi_master: total 0 lrwxrwxrwx 1 root root 0 Jun 17 14:17 spi6 -> ../../devices/platform/interconnect@100000/2160000.spi/spi_master/spi6
/sys/class/spidev: total 0 lrwxrwxrwx 1 root root 0 Jun 17 14:17 spidev6.0 -> ../../devices/platform/interconnect@100000/2160000.spi/spi_master/spi6/spi6.0/spidev/spidev6.0