SBAA535A March   2022  – March 2024 ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1013-Q1 , ADS1014 , ADS1014-Q1 , ADS1015 , ADS1015-Q1 , ADS1018 , ADS1018-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1113-Q1 , ADS1114 , ADS1114-Q1 , ADS1115 , ADS1115-Q1 , ADS1118 , ADS1118-Q1 , ADS1119 , ADS1120 , ADS1120-Q1 , ADS112C04 , ADS112U04 , ADS1130 , ADS1131 , ADS1146 , ADS1147 , ADS1148 , ADS1148-Q1 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1158 , ADS1216 , ADS1217 , ADS1218 , ADS1219 , ADS1220 , ADS122C04 , ADS122U04 , ADS1230 , ADS1231 , ADS1232 , ADS1234 , ADS1235 , ADS1235-Q1 , ADS1243-HT , ADS1246 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS1250 , ADS1251 , ADS1252 , ADS1253 , ADS1254 , ADS1255 , ADS1256 , ADS1257 , ADS1258 , ADS1258-EP , ADS1259 , ADS1259-Q1 , ADS125H01 , ADS125H02 , ADS1260 , ADS1260-Q1 , ADS1261 , ADS1261-Q1 , ADS1262 , ADS1263 , ADS127L01 , ADS1281 , ADS1282 , ADS1282-SP , ADS1283 , ADS1284 , ADS1287 , ADS1291 , LMP90080-Q1 , LMP90100 , TLA2021 , TLA2022 , TLA2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Data Sheet Timing and Nomenclature
  6. 3 What Causes Conversion Latency in a Delta-Sigma ADC?
  7. 4 Digital Filter Operation and Behavior
    1.     8
    2.     9
    3. 4.1 Unsettled Data Due to an ADC Operation
  8. 5 ADC Features and Modes that Affect Conversion Latency
    1. 5.1 First Conversion Versus Second and Subsequent Conversion Latency
    2. 5.2 Conversion Mode
    3. 5.3 Programmable Delay
    4. 5.4 ADC Overhead Time
    5. 5.5 Clock Frequency
    6. 5.6 Chopping
  9. 6 Analog Settling
  10. 7 Important Takeaways
  11. 8 Cycle Time Calculation Examples
    1. 8.1 Example #1: Using the ADS124S08
    2. 8.2 Example #2: Changing the Conversion Mode
    3. 8.3 Example #3: Changing the Filter Type
    4. 8.4 Example #4: Changing the Clock Frequency
    5. 8.5 Example #5: Enabling Chop and Reducing the Number of Conversions per Channel
    6. 8.6 Example #6: Scanning Two Channels With Different System Parameters
    7. 8.7 Example #7: Using the ADS1261
    8. 8.8 Example #8: Changing Multiple Parameters Using the ADS1261
  12. 9 Summary
  13. 10Revision History

8.8 Example #8: Changing Multiple Parameters Using the ADS1261

Table 8-8 reports the system parameters that determine the cycle time in Example #8:

Table 8-8 System Parameters for Example #8
PARAMETERVALUE
ADCADS1261
ODR600 SPS
Filter typesinc2
Clock frequency4 MHz
Conversion modePulse-convert
Programmable delay<Not default - see example description>
ChoppingEnabled
Conversions per channel2
# of channels2

Example #8 uses the same ADC from Example #7 (ADS1261), though almost all of the system parameters have been changed. These changes include a 60-SPS ODR, a sinc2 filter, a 4-MHz clock frequency (fCLK_NEW), pulse-convert mode (similar to single-shot mode), chopping enabled, and two conversion results per channel instead of three. Additionally, the programmable delay has been changed from the default value, though the specific value in milliseconds depends on the clock frequency and is calculated during the example.

Similar to Example #5 where chop was enabled using single-shot mode, both conversion results on each channel using the new example parameters require two first-conversion latency periods. Table 2-2 identifies that the first conversion latency, tFC, is 33.76 ms for the ADS1261 using the sinc2 filter and ODR = 60 SPS. In this case, tFC is derived using the default clock frequency, fCLK, of 7.3728 MHz and includes the default 50-µs programmable delay, tDELAY_DEFAULT. It is therefore necessary to scale tFC based on fCLK_NEW = 4 MHz and apply the new programmable delay.

Unlike the ADS124S08, the ADS1261 data sheet only provides tFC in milliseconds, not tMOD periods. To translate to a new conversion latency value, tFC_NEW, first remove tDELAY_DEFAULT. Then, scale tFC by the ratio of fCLK to fCLK_NEW as per Equation 35:

Equation 35. tFC_NEW = (tFC – tDELAY_DEFAULT) ∙ (fCLK / fCLK_NEW)

Applying the values from this example yields a value for tFC_NEW given by Equation 36:

Equation 36. tFC_NEW = (33.76 ms – 0.05 ms) ∙ (7.3728 MHz / 4 MHz) = 62.134 ms

The programmable delay options in the ADS1261 are also specified in milliseconds and referenced to fCLK. Perform a similar operation as shown in Equation 36 to scale any new programmable delay value, tDELAY_NEW, for fCLK_NEW. For this example, choose a nominal programmable delay, tDELAY_NOM, of 328 µs from the MODE1 register in the ADS1261 data sheet. Then, scale tDELAY_NOM by the ratio of fCLK to fCLK_NEW to get a value for tDELAY_NEW as per Equation 37:

Equation 37. tDELAY_NEW = tDELAY_NOM ∙ (fCLK_NOM / fCLK_NEW)

In this example, tDELAY_NEW = 328 µs ∙ (7.3728 MHz / 4 MHz) = 0.605 ms. As a result, the total conversion latency, tFC_TOTAL, is given by Equation 38:

Equation 38. tFC_TOTAL = tFC_NEW + tDELAY_NEW = 62.134 ms + 0.605 ms = 62.739 ms

As stated previously, chopping requires two first-conversion latency periods (2 ∙ tFC_TOTAL) per conversion result. With two conversion results per channel and assuming that the user starts the next conversion immediately after the previous conversion result is ready, Equation 40 calculates the cycle time, tCYCLE, using the scan time for one channel, tCH, that results from Equation 39:

Equation 39. tCH = 2 ∙ (2 ∙ tFC_TOTAL) = 4 ∙ 62.739 ms = 250.956 ms
Equation 40. tCYCLE = # of channels ∙ tCH = 2 ∙ 250.956 ms = 501.912 ms

Ultimately, the cycle time for this example is 501.912 ms for 4 conversion results. Figure 8-9 depicts a timing diagram for the example system given the design parameters.

GUID-20220201-SS0I-BLCQ-0Z53-J4M3RQCHND3Z-low.svgFigure 8-9 Timing Diagram for Example #8