SBAA535A March 2022 – March 2024 ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1013-Q1 , ADS1014 , ADS1014-Q1 , ADS1015 , ADS1015-Q1 , ADS1018 , ADS1018-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1113-Q1 , ADS1114 , ADS1114-Q1 , ADS1115 , ADS1115-Q1 , ADS1118 , ADS1118-Q1 , ADS1119 , ADS1120 , ADS1120-Q1 , ADS112C04 , ADS112U04 , ADS1130 , ADS1131 , ADS1146 , ADS1147 , ADS1148 , ADS1148-Q1 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1158 , ADS1216 , ADS1217 , ADS1218 , ADS1219 , ADS1220 , ADS122C04 , ADS122U04 , ADS1230 , ADS1231 , ADS1232 , ADS1234 , ADS1235 , ADS1235-Q1 , ADS1243-HT , ADS1246 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS1250 , ADS1251 , ADS1252 , ADS1253 , ADS1254 , ADS1255 , ADS1256 , ADS1257 , ADS1258 , ADS1258-EP , ADS1259 , ADS1259-Q1 , ADS125H01 , ADS125H02 , ADS1260 , ADS1260-Q1 , ADS1261 , ADS1261-Q1 , ADS1262 , ADS1263 , ADS127L01 , ADS1281 , ADS1282 , ADS1282-SP , ADS1283 , ADS1284 , ADS1287 , ADS1291 , LMP90080-Q1 , LMP90100 , TLA2021 , TLA2022 , TLA2024
Table 8-8 reports the system parameters that determine the cycle time in Example #5:
PARAMETER | VALUE |
---|---|
ADC | ADS124S08 |
ODR | 1000 SPS |
Filter type | Low-latency |
Clock frequency | 4.096 MHz (default) |
Conversion mode | Single-shot |
Programmable delay | 14 ∙ tMOD (default) |
Chopping | Enabled |
Conversions per channel | 2 |
# of channels | 2 |
Example #5 is similar to Example #3, though in this case the ADS124S08 chopping feature is turned on. Also, the number of conversions per channel has been reduced from 3 to 2. When chopping is enabled and single-shot mode is used, two conversions must be averaged to generate each conversion result. This increases the overall conversion latency.
While not shown in this document, the ADS124S08 data sheet identifies the first-conversion latency, tFC, using the low-latency filter at ODR = 1000 SPS as 1.156 ms. This time includes the ADC overhead but does not include the programmable delay, tDELAY.Equation 22 calculates the value of tDELAY in microseconds using the default value of tDELAY = 14 ∙ tMOD and fCLK = 4.096 MHz:
The ADS124S08 programmable delay applies to each conversion using single-shot mode, resulting in a first conversion latency including programmable delay, tFC_TOTAL, as per Equation 23:
Finally, there is a need to consider additional latency due to chopping because each output is an average of two conversions. Since producing each conversion using single-shot mode requires 1 ∙ tFC_TOTAL, a single conversion result with global chop enabled requires 2 ∙ tFC_TOTAL. Equation 25 calculates the cycle time, tCYCLE, using the scan time for one channel, tCH, that results from Equation 24. This assumes that the user starts the next conversion on each channel immediately after the previous conversion result is ready:
Ultimately, the cycle time for this example is 9.688 ms for 4 conversion results. Figure 8-5 depicts a timing diagram for the example system given the design parameters.