SBAA565 November   2022 ADC081C021 , ADC081C027 , ADC101C021 , ADC101C027 , ADC121C021 , ADC121C021-Q1 , ADC121C027 , ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1014 , ADS1015 , ADS1015-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1114 , ADS1115 , ADS1115-Q1 , ADS7823 , ADS7827 , ADS7828 , ADS7828-Q1 , ADS7830 , ADS7924 , AFE539A4 , DAC081C081 , DAC081C085 , DAC101C081 , DAC101C081Q , DAC101C085 , DAC121C081 , DAC121C085 , DAC43204 , DAC43401 , DAC43401-Q1 , DAC43608 , DAC43701 , DAC43701-Q1 , DAC53002 , DAC53004 , DAC53202 , DAC53204 , DAC53204W , DAC53401 , DAC53401-Q1 , DAC53608 , DAC53701 , DAC53701-Q1 , DAC5571 , DAC5573 , DAC5574 , DAC5578 , DAC60501 , DAC60502 , DAC63002 , DAC63004 , DAC63202 , DAC63204 , DAC6571 , DAC6573 , DAC6574 , DAC6578 , DAC70501 , DAC70502 , DAC7571 , DAC7573 , DAC7574 , DAC7578 , DAC7678 , DAC80501 , DAC80502 , DAC8571 , DAC8574

 

  1.   Abstract
  2.   Trademarks
  3. 1I2C Overview
    1. 1.1 History
    2. 1.2 I2C Speed Modes
  4. 2I2C Physical Layer
    1. 2.1 Two-Wire Communication
    2. 2.2 Open-Drain Connection
    3. 2.3 Non-Destructive Bus Contention
  5. 3I2C Protocol
    1. 3.1 I2C START and STOP
    2. 3.2 Logical Ones and Zeros
    3. 3.3 I2C Communication Frames
  6. 4I2C Examples
    1. 4.1 DAC80501 Example
      1. 4.1.1 DAC80501 DAC Data Register
      2. 4.1.2 DAC80501 I2C Example Write
    2. 4.2 ADS1115 Example
      1. 4.2.1 ADS1115 Configuration Register
      2. 4.2.2 ADS1115 I2C Example Read
      3. 4.2.3 ADS1115 Conversion Result
  7. 5Reserved Addresses
    1. 5.1 General Call
    2. 5.2 START Byte
    3. 5.3 C-Bus Address, Different Bus Format, Future Purposes
    4. 5.4 HS-Mode Controller Code
    5. 5.5 Device ID
    6. 5.6 10-Bit Target Addressing
      1. 5.6.1 10-Bit Target Addressing Write
      2. 5.6.2 10-Bit Target Addressing Read
  8. 6Advanced Topics
    1. 6.1 Clock Synchronization and Arbitration
    2. 6.2 Clock Stretching
    3. 6.3 Electrical Specifications
    4. 6.4 Voltage Level Translation
      1. 6.4.1 Example 1
      2. 6.4.2 Example 2
      3. 6.4.3 Example 3
      4. 6.4.4 Example 4
    5. 6.5 Pullup Resistor Sizing
      1. 6.5.1 Minimum Pullup Resistance Sizing
      2. 6.5.2 Maximum Pullup Resistance Sizing
  9. 7Protocols Similar to I2C
  10. 8Summary

6.1 Clock Synchronization and Arbitration

The first I2C topic in this section is clock synchronization and arbitration between controller devices on the bus. In I2C, there can be multiple controllers on the same bus. Because of this, there can be two or more devices trying to claim the bus for communication at the same time. This requires multiple active controllers to resolve which device controls the bus.

Figure 6-1 I2C Bus Contention With Multiple Controllers

I2C uses a method of clock synchronization and arbitration to make sure that one controller gains control and does so without compromising communication. Because I2C uses open-drain connections to SDA and SCL, the connections result in a wired-AND connection, where the line gives a logical AND of the device outputs. This is helpful in arbitration without disruption to the communication. In systems with only one controller, this arbitration is not necessary.

This section details clock synchronization and how multiple controllers synchronize clocks for I2C to prevent contention. How controllers use arbitration to determine which controller wins the bus without disruptive contention is also described.

To prevent bus contention, clock synchronization is first performed using the SCL line and the open-drain connections from the controllers on the bus. This wired-AND connection is low if any of the controllers pull SCL low. This connection is the logical AND of the SCL connection of the two controller devices. The output of SCL is high only if both controller devices have released the open-drain connection high. Table 6-1 details a truth table of this logical wired-AND.

Table 6-1 Wired-AND Truth Table
Controller 1 SCL Controller 2 SCL Resulting SCL
0 0 0
0 1 0
1 0 0
1 1 1

During a START condition where two controllers are trying to claim the bus, there is a high-to-low transition on SCL. Here is an example where two controller devices are trying to claim the bus at or near the same time.

In Figure 6-2, the controller 1 device initiates a START condition shortly before controller device 2 does the same. Controller 1 pulls SCL down before controller 2. With the wired-AND connection, SCL pulls low as soon as controller 1 pulls down on SCL.

Figure 6-2 I2C Clock Synchronization SCL Going Low

After the START condition, controller 1 releases SCL to go high. However, controller 2 is still holding SCL low. Because of the wired-AND connection, SCL remains low until controller 2 releases the SCL high. At the same time, controller 1 is still monitoring SCL and must wait for the other controller to release the clock. Controller 1 cannot advance the SCL pulse until controller 2 has released SCL and becomes available.

When multiple controllers are competing for the bus, SCL stays low for as long as the longest period of time that any controller pulls down SCL. Only after all the controllers have released the SCL can the line be released high for the serial clock pulse. This synchronizes the start of the serial clock for all controllers. Figure 6-3 shows the resulting SCL as both controllers release the SCL.

Figure 6-3 I2C Clock Synchronization SCL Returning High

For clock synchronization, each controller device must monitor the SCL line and react to cases where the SCL does not match the expected SCL output.

Similarly, after the beginning of the serial clock pulse, all the controllers pull down on SCL to complete the serial clock pulse. Again, with the wired-AND connection, SCL is then pulled down with the first controller that responds by pulling down SCL. The first controller that completes the SCL high-time period determines the high time of SCL from the wired-AND connection. Figure 6-4 shows the SCL line as SCL is again pulled low.

Figure 6-4 I2C Clock Synchronization Monitoring SCL

The synchronization of the SCL clock continues for subsequent clock pulses between all active controllers. Each SCL clock pulse is generated with the low period determined by the controller with the longest clock low period and the high period is determined by the controller with the shortest clock high period. Clock synchronization continues through the communication shown in Figure 6-5.

Figure 6-5 I2C Clock Synchronization Resulting Wired-And

Clock synchronization works because the controllers monitor each pulse of the SCL line and react to cases where the SCL line does not match the state that the controller expects.

Now that the serial clocks are synchronized, arbitration is done on SDA. Both controllers transmit data normally on SDA, sending their communication to the intended target device. Similar to SCL, SDA is a wired-AND connection. Figure 6-6 shows arbitration of SDA after clock synchronization.

Figure 6-6 I2C Controller Arbitration

In bus arbitration, the communication continues until there is a noted difference between the data being sent.

In the figure, both devices send the I2C START at the same time. For the first two bits of the transmission, the data are the same. After the data reaches the third bit, there is a difference as controller 1 sends a 0, while controller 2 sends a 1. Because both controllers monitor the SDA and SCL lines, the contention is discovered. Controller 2 discovers that SDA is low despite sending a 1. To preserve the communication on the bus with the correct wired-AND result, controller 2 releases the bus, while controller 1 wins the arbitration.