SLAAE56A November   2022  – March 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of STM32 MCUs to MSPM0 MCUs
  4. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 CubeIDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 CubeMX vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  5. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
    6. 3.6 Interrupt and Events Comparison
    7. 3.7 Debug and Programming Comparison
  6. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  7. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  8. 6Revision History

3.3 Power Up and Reset Summary and Comparison

Similar to STM32G0 devices, MSPM0 devices have a minimum operating voltage and have modules in place to make sure that the device starts up properly by holding the device or portions of the device in a reset state. Table 3-4 shows a comparison on how this is done between the two families and what modules control the power up process and reset across the families.

Table 3-4 Comparison of Power up
STM32G0 Devices MSPM0 Devices
Modules governing power up and resets PWR (power) and RCC (Reset and Clock Control) modules Module governing power up and resets PMCU (Power Management and Clock Unit)
Voltage-Level Based Resets
POR (Power-On Reset) Complete device reset. First level voltage release for power up. Lowest voltage level for power down. POR (Power-On Reset) Complete device reset. First level voltage release for power up. Lowest voltage level for power down.
BOR (Brownout Reset) with configurable levels Sometimes programmable. Set voltage level that releases reset state on power up, or resets device on power down. Configurable BOR (Brownout Reset) Can be configured as a reset or interrupt, with different voltage thresholds, combining the functionality of the STM32G0 BOR and PVD.
PVD (Programmable Voltage Detector) Configurable voltage monitor that can provide interrupts.

STM32G0 defines different reset domains, while MSPM0 devices have different levels of reset states. For MSPM0 devices, the reset levels have a set order, and when a level is triggered, all subsequent levels are reset until the device is released into RUN mode. Table 3-5 gives a brief description and comparison between STM32G0 reset domains and MSPM0 reset states. #GUID-D14F0E25-5973-4349-9966-B9316B34CA29 shows the relationship between all of the MSPM0 reset states.

Table 3-5 Comparison of Reset Domains
STM32G0 Reset Domains

MSPM0 Reset States#LI_MPK_FWV_HVB
Power reset domain Typical triggers are POR, BOR, and exits from standby or shutdown modes. All registers reset except those outside VCORE domain. POR Typical triggers: POR voltage levels, SW trigger, NRST held low for >1s. Resets shutdown memory, re-enables NRST and SWD, triggers BOR
BOR Typical triggers: POR or BOR voltage level, exit from shutdown mode. Resets PMU, VCORE, and associated logic. Triggers BOOTRST.
No exact equivalent. Boot configuration is read on the fourth clock cycle of SYSCLK after a reset. Boot reset (BOOTRST) Typical triggers: BOR or software trigger, fatal clock failure, NRST held low for <1 s. Executes boot configuration routine. Resets majority of core logic and registers, including RTC, clock, and IO configurations.#LI_GB2_GWV_HVB SRAM power cycled and lost. Triggers SYSRST.
System reset domain System reset sets all registers to their reset values except the reset flags in the clock control and status register (RCC_CSR) and the registers in the RTC domain. System reset (SYSRST) Typical triggers: BOOTRST, BSL entry or exit, watchdog timer, software trigger, debug subsystem. Resets CPU state and all peripherals except RTC, LFCLK, LFXT, and SYSOSC frequency correction loop. Device enters RUN mode on exit.
No equivalent CPU-only reset (CPURST) Software and debug subsystem triggers only. Resets CPU logic only. Peripheral state are not affected.
RTC domain Triggered by software or VDD or VBAT power on, if both supplies where previously been powered off. Resets only the LSE oscillator, RTC, backup registers and RCC RTC domain control register. RTC and associated clocks are reset through BOOTRST, BOR, or POR.#LI_GB2_GWV_HVB
(1) Not all reset triggers described. Refer to the PMCU chapter of the device TRM for all available reset triggers.
(2) If BOOTRST cause was through NRST or software trigger, RTC, LFCLK, and LFXT/LFLCK_IN configurations and IOMUX settings are NOT reset to allow RTC to maintain operation through external reset.
Figure 3-1 MSPM0 Reset Levels