SLAAE56A November   2022  – March 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of STM32 MCUs to MSPM0 MCUs
  4. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 CubeIDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 CubeMX vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  5. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
    6. 3.6 Interrupt and Events Comparison
    7. 3.7 Debug and Programming Comparison
  6. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  7. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  8. 6Revision History

3.1 CPU

The STM32G0 and MSPM0 family of parts are both based on the Arm Cortex® M0+ CPU core architecture and instruction set. The table below gives a high-level overview of the general features of the CPUs in the MSPM0G and MSPM0L families compared to the STM32G0. Interrupts and Exceptions provides a comparison of the interrupts and exceptions and how they are mapped in the Nested Vectored Interrupt Controller (NVIC) peripheral included in the M0 architecture for each device.

Table 3-1 Comparison of CPU Feature Sets
FeatureSTM32G0MSPM0GMSPM0L
ArchitectureArm Cortex-M0+Arm Cortex-M0+Arm Cortex-M0+
Maximum MCLK64 MHz80 MHz32 MHz
CPU instruction cache2x64 bit lines (16 bytes)4x64 bit lines (32 bytes)2x64-bit lines (16 bytes)
Processor trace capabilitiesNoYes, integrated micro trace bufferNo
Memory protection unit (MPU)YesYesNo
System timer (SYSTICK)YesYes - 24 bitYes - 24 bit
NVM prefetchYesYesYes
Hardware multiply

Yes

YesYes
Hardware breakpoint / watchpoints4 / 24 / 24 / 2
Boot routine storageFlash (system memory)ROMROM
Bootstrap loader storageFlash (system memory)ROMROM
Bootloader interface support(1)(2)UART, I2C, SPI, USB, FDCANUART, I2C, user extendable UART, I2C,

user extendable

DMAYesYesYes
(1) Refer to the device-specific data sheet for availability.
(2) Other interfaces to be made available in later device releases.