SLAAE56A November 2022 – March 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1
The MSPM0 and STM32G0 family of MCUs feature nonvolatile flash memory used for storing executable program code and application data.
Features | STM32G0 | MSPM0 |
---|---|---|
Flash memory |
STM32G0B1xx, G0C1xx (up to 512KB) STM32G071xx, G081xx (up to 128KB) STM32G031xx, G041xx, G051xx, G061xx (up to 64KB) |
MSPM0Gx x ranges 128KB to 32KB MSPM0Lxx ranges 64KB to 8KB |
Memory organization |
1 bank – devices up to 128KB 2 banks – devices with >128KB |
1 bank – devices up to 256KB 2 banks – devices with >256KB |
Flash wait states |
0 (HCLK ≤ 24 MHz) 1 (HCLK ≤ 48 MHz) 2 (HCLK ≤ 64 MHz) |
0 (MCLK, CPUCLK ≤ 24 MHz) 1 (MCLK, CPUCLK ≤ 48 MHz) 2 (MCLK, CPUCLK ≤ 80 MHz) |
Flash word size | 64 bits plus 8 ECC bits | Same |
Programming resolution | Single word size | Single word, 32-, 16-, or 8-bit (byte) |
Multi-word programming | 32 words (256 bytes) | 2, 4, or 8 words (up to 64 bytes) |
Erase |
Page size = 2KB Bank erase (single bank) Mass erase (all banks) |
Sector size = 1KB Bank erase (up to 256KB) |
Write protection | Yes (2 write protection areas per bank) | Yes, static and dynamic |
Read protection | Yes | Yes |
Flash memory read operations | 64-bit flash word size plus 8 ECC bits | Same – if optional ECC is present |
Flash memory write operations | 64-bit flash word size plus 8 ECC bits | Same – if optional ECC is present |
Error code correction (ECC) | 8 bits for 64 bits | Same |
Securable memory area | Yes, main memory | No |
Info memory | Yes | Yes (NONMAIN) |
OTP data region | 1KB | No |
Prefetch | Yes | Yes |
CPU instruction cache |
Two 64-bit cache lines (16 bytes) 4x 32-bit instructions or 8x 16-bit instructions |
Four 64-bit cache lines (32 bytes) 8x 32-bit instructions or 16x 16-bit instructions |
In addition to the flash memory features listed in the previous table, the MSPM0 flash memory also has the following features: