SLVA504A February   2012  – July 2021 DRV8243-Q1 , DRV8244-Q1 , DRV8245-Q1 , DRV8800 , DRV8801 , DRV8802 , DRV8803 , DRV8804 , DRV8805 , DRV8806 , DRV8811 , DRV8812 , DRV8813 , DRV8814 , DRV8818 , DRV8821 , DRV8823 , DRV8824 , DRV8825 , DRV8828 , DRV8829 , DRV8830 , DRV8832 , DRV8832-Q1 , DRV8833 , DRV8834 , DRV8835 , DRV8836 , DRV8837 , DRV8840 , DRV8841 , DRV8842 , DRV8843 , DRV8844 , DRV8870 , DRV8871 , DRV8872

 

  1. 1Sources of Power Dissipation in an Integrated Driver
    1. 1.1 H-Bridge
      1. 1.1.1 H-Bridge Driver Using High-Side Recirculation
      2. 1.1.2 H-Bridge Driver Using Low-Side Recirculation
    2. 1.2 Half Bridge
      1. 1.2.1 Half Bridge Driver Using High-Side Recirculation
      2. 1.2.2 Half Bridge Driver Using Low-Side Recirculation
  2. 2Example Calculation
    1. 2.1 H-Bridge
      1. 2.1.1 High-Side Recirculation Example
      2. 2.1.2 Low-Side Recirculation Example
    2. 2.2 Half Bridge
      1. 2.2.1 Half-Bridge High-Side Recirculation Example
      2. 2.2.2 Half-Bridge Low-Side Recirculation Example
  3. 3References
  4. 4Revision History

1.1.1 H-Bridge Driver Using High-Side Recirculation

Figure 1-1 H-Bridge Using High-Side Recirculation

Figure 1-1 shows the switching sequence of a full bridge in PWM regulation between HS1 - load - LS2 (region # 1) and HS1 - load - HS2 (region # 5) with other transitions (region # 2, 3, and 4 for rising edge and region # 6, 7, 8 for falling edge). The power dissipation on each FET is as follows:

Table 1-1 Power Dissipation for H-Bridge with High-Side Recirculation
Region Time ratio within PWM cycle HS1 [W] LS1 [W] HS2 [W] LS2 [W]
1 D = On-time × fPWM1 RON × IL2 0 0 RON × IL2
2 VM/SRLSOFF x fPWM RON × IL2 0 0 0.5 x VM x IL
3 tDEAD_LSOFF x fPWM RON × IL2 0 VD x IL 0
4 VD/SRHSON x fPWM RON × IL2 0 0.5 x VD x IL 0
5 (1 - D) = Off-time × fPWM1 RON × IL2 0 RON × IL2 0
6 VD/SRHSOFF x fPWM RON × IL2 0 0.5 x VD x IL 0
7 tDEAD_LSON x fPWM RON × IL2 0 VD x IL 0
8 VM/SRLSON x fPWM RON × IL2 0 0 0.5 x VM x IL
  1. If the slew time is significant portion of the PWM period, we recommend to adjust the duty cycle number based on slew times for regions # 1 and 5.

In Table 1-1,

  1. RON = FET on-resistance [ohm]
  2. fPWM = PWM switching frequency [Hz]
  3. VM = Supply voltage to the driver [V]
  4. IL = Load current [A]
  5. D = PWM duty cycle [a fractional number between 0 and 1]
  6. SRLSOFF = Output voltage slew rate during rise when LS2 is turned off [V/sec]
  7. SRLSON = Output voltage slew rate during fall when LS2 is turned on [V/sec]
  8. VD = FET body diode forward bias voltage [V]
  9. tDEAD_LSOFF = dead time after LS2 has been turned off [sec]
  10. tDEAD_LSON = dead time before LS2 is turned on [sec]
  11. SRHSON = Output voltage slew rate during rise when HS2 is turned on [V/sec]
  12. SRHSOFF = Output voltage slew rate during fall when HS2 is turned off [V/sec]

If we assume power dissipation in regions #4 and #6 are negligible, slews rate match for rising and falling edges, dead times are equal, then power dissipation for each FET can be approximated as follows:

  1. PHS1 = RON × IL2
  2. PLS1 = 0
  3. PHS2 = [RON × IL2 x (1-D)] + [2 x VD x IL x tDEAD x fPWM]
  4. PLS2 = [RON × IL2 x D] + [VM x IL x (VM / SR) x fPWM]

For estimating power dissipation for load current flow in the reverse direction, identical equations apply, with only swapping of HS1 with HS2 and LS1 with LS2.