The Programmable Real-time Unit (PRU) is a small processor core that is tightly integrated with an IO subsystem, offering low-latency control of IO pins. The TI Sitara family of devices offer three flavors of PRU Subsystem.

The Programmable Real-time Unit and Industrial Communication Subsystem (PRU-ICSS) consists of dual 32-bit RISC cores (the PRUs), shared data, instruction memories, internal peripheral modules, and an interrupt controller (INTC). The programmable nature of the PRU, along with its access to pins (IOs), events and all System-on-Chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC.

Devices offering the PRU-ICSS capability include AM263x, AM335x, AM437x, AM57x and K2G.

The Programmable Real-time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) can be considered a superset of the PRU-ICSS. In addition to all PRU-ICSS features, the PRU_ICSSG adds two Auxiliary Programmable Real-Time Unit (RTU) cores, two Transmit PRU (TX_PRU) cores, broadside memories, improved event management with the task manager, data processing and data movement accelerators, and new peripherals such as PWM.

Devices offering the PRU_ICSSG capability include AM65x, AM64x and AM243x.