SPRAC90G August   2021  – October 2022 66AK2G12 , AM2431 , AM2432 , AM2434 , AM2631 , AM2632 , AM2634 , AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359 , AM4372 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM623 , AM625 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548

 

  1.   PRU-ICSS Feature Comparison
  2.   Trademarks
  3. 1Introduction
    1. 1.1 PRU-ICSS: The Programmable Real-time Unit and Industrial Communication Subsystem
    2. 1.2 PRU_ICSSG: The Programmable Real-time Unit and Industrial Communication Subsystem - Gigabit
    3. 1.3 PRUSS: The Programmable Real-time Unit Subsystem
    4. 1.4 PRU Subsystem Feature Comparison
  4. 2PRU-ICSS Feature Comparison
  5. 3PRU_ICSSG Feature Comparison
  6. 4PRUSS Features
  7. 5References
  8. 6Revision History

3 PRU_ICSSG Feature Comparison

Table 3-1 summarizes the PRU_ICSSG features.

Table 3-1 PRU_ICSSG Feature Comparison Across Devices
Feature AM65x SR1.0 AM65x SR2.0 AM64x/AM243x
General PRU Specifications Subsystem type 3x PRU_ICSSG 2x PRU_ICSSG
Number of PRU cores 2
Number of RTU_PRU (Auxiliary PRU) cores 2
Number of TX_PRU (Transmit PRU) cores 0 2
Max Frequency 250 MHz 333 MHz
IRAM Size (per PRU / RTU_PRU / TX_PRU core) 12 KB (w/ECC) / 8 KB (w/ ECC) / 0 KB 12 KB (w/ ECC) / 8 KB (w/ ECC) / 6 KB (w/ ECC)
DRAM Size (2 DRAMs per PRU_ICSSG) 8 KB (w/ ECC)
Shared DRAM Size 64 KB (w/ ECC)
INTC Yes
General Purpose Inputs (per PRU core) Direct; or 16-bit parallel capture; or 28-bit shift; or 3 ch EnDat 2.2; or 9 ch Sigma Delta
General Purpose Outputs (per PRU core) Direct or Shift out
GPI Pins (PRU0, PRU1) PRU_ICSSG0: 20/20
PRU_ICSSG1: 20/20
PRU_ICSSG2: 18/18 (1) N/A
GPO Pins (PRU0, PRU1) PRU_ICSSG0: 20/20
PRU_ICSSG1: 20/20
PRU_ICSSG2: 18/18 (1) N/A
Accelerators: Data Processing     MPY/MAC Yes
    CRC 16/32 Yes
    Scratch Pad

Yes

(PRU cores: 4 banks, RTU_PRU cores: 2 banks)

Yes

(PRU cores: 3 banks, RTU_PRU cores: 3 banks, TX_PRU cores: 2 banks)
    IPC Scratch Pad Yes
    Broadside RAM 4 KB 2 KB
    BSWAP Yes
    SUM32 Yes
    Task Manager Yes
    Spinlock Yes
    Filter Data Base (FDB) Yes
Accelerators: Data Movement     XFR2VBUS Yes
    PSI TX & RX Yes
    XFR2TR Yes
Peripherals     UART 1
    eCAP 1
    IEP 2
    MII_G_RT (MII/RGMII) 2
    MDIO 1
    SGMII 2 (PRU_ICSSG2 instance only) No
    PWM 12 primary and 12 complimentary outputs
(1) PRG2_PRU0/1_GPI/O17 does not have a ball named after it, but it is still muxed out