SPRADC3 june   2023 AM2431 , AM2432 , AM2434 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1 , AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3358-EP , AM3359 , AM4372 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM5749 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to 8b-10b Line Coding
  5. 2PRU Implementation for Data Transmitting and Receiving
    1. 2.1 Encoding and Decoding Data
    2. 2.2 PRU Module Interface and GPIO Mode
    3. 2.3 PRU GPIO Shift-out and Shift-in Mode for Communication
    4. 2.4 Three-channel Peripheral Interface for Communication
    5. 2.5 LVDS and M-LVDS Interface
  6. 3System Solution With CRC Module and Over-head Optimization
    1. 3.1 PRU CRC16/32 Module
    2. 3.2 Encode and Decode Over-head Optimization
  7. 4Verification
  8. 5Summary
  9. 6References

2.2 PRU Module Interface and GPIO Mode

The PRU module interface consists of the PRU internal registers 30 and 31 (R30 and R31). Figure 2-3 shows the PRU module interface and the functionality of R30 and R31. Register R31 serves as an interface between the dedicated PRU general purpose input (GPI) pins and the PRU Interrupt controller (INTC). Reading R31 returns status information from the GPI pins and PRU INTC using the PRU Real Time Status Interface. Writing to R31 generates PRU system events through the PRU Event Interface. Register R30 serves as an interface with the dedicated PRU general purpose output (GPO) pins.

GUID-20230606-SS0I-DX22-H52Z-QWMLHSJHKC1S-low.svg Figure 2-3 PRU Module Interface

The PRU Event Interface directly sends pulsed event information out of the internal Arithmetic and Logic Unit (ALU) of the PRU. These events are exported out of the PRU and need to be connected to the system interrupt controller at the System on Chip (SoC) level. The event interface can be used by the firmware to create software interrupts from the PRU to the Arm® core (host processor). For example, the event can be generated when the communication frame package completes to signal the Arm® for an interrupt.

The PRU implements an enhanced general-purpose input or output (GPIO) module that supports the following general-purpose input modes: direct input, 16-bit parallel capture, 28-bit serial shift in, and MII_RT (Ethernet MAC Interface). Register R31 serves as an interface with the general-purpose inputs. R31 also supports two general-purpose output modes: direct output and shift out. Register R30 serves as an interface with the general-purpose outputs.